资源列表
C2Mif
- 。.mif文件生成器 FPGA rom 的生成-producer of .mif file
wei_xulie
- 为序列发生器，数字系统传输性能分析设计，做眼图测试用-Sequence generator, digital transmission performance of system analysis and design, make eye test
singen
- 利用vhdl在quartusii中编写的正弦信号发生器，并在quartusii中进行了仿真-Using the VHDL in a QuartusII in the preparation of the sinusoidal signal generator, and makes simulation in QuartusII
dds_wave
- 基于数字频率合成技术DDS，在quartusii编写相关代码，实现正弦信号输出，同时可以实现调幅、调频和数码管闲事-Based on the digital frequency synthesis technology of DDS, written in QuartusII code, achieve sinusoidal signal output, and can achieve amplitude modulation, frequency modulation and digital
RISC_CPU
- VHDL语言设计的RISC_CPU，分为八个基本部件分模块构建，分别为时钟发生器，指令寄存器，累加器，算术逻辑运算单元，数据控制器，状态控制器，程序计数器以及地址多路器-The VHDL language RISC_CPU, is divided into eight basic components of modular construction, respectively, the clock generator, the instruction register, accumulator,
901_1
- 里面包含曼彻斯特编解码的大概描述及用Verilog编写的代码。-Which contains the Manchester encoding and decoding is probably described and written in Verilog code.
USART
- RS232串口通信的VERILOG代码，包含了测试文件，及参数文件，用户只需要修改参数文件里的参数即可满足不同的应用需求；由于串口逻辑比较简单，程序中没有注释；-RS232 serial communication VERILOG code contains the test files and parameter files, users only need to modify the parameters in the parameter file to meet different app
clock
- 在Quartus II环境下开发了一个多功能数字时钟，是一个完整的工程，包含仿真和编程下载文件。-In Quartus II environment developed a multi-function digital clock, is a complete project, including the simulation and programming download files.
FPGAMp3Player_MihaiAndreiVeres
- 使用VHDL语言实现MP3播放，和SD卡的SPI模式交互，以及文件系统的实现-MP3 player, and SD card SPI mode interaction, as well as file system using VHDL
dc-motor-speed-control
- 基于VHDL的pwm直流电动机双闭环调速-Pwm dc motor speed control based on VHDL
dds
- 自己写的dds工程文件，用的VHDl,三角波，方波。正玄波-Dds engineering documents, write your own used VHDl, triangle wave, square wave. Positive sine wave
VerilogHDL
- 比较详实的介绍了verilonghdl语言，是一本不可多得书籍-More detailed descr iption of the the verilonghdl language, is a rare books ~ ~ ~