资源列表
timing
- 对输入CPLD/FPGA特定口的前后两个脉冲间隔进行计数并输出-timing for the break of 2 impulses into the certain input of CPLD/FPGA and output
mjoy_v1.1
- aeromodelling software
Synplify901.crack
- 高性能综合工具Synplify9.0.1破解文件-High-performance integrated tool Synplify9.0.1 crack file
URAT-VHDL
- vhdl版本的uart收发程序，方便实用-uart vhdl rx/tx
lcd-1602
- 关于用4端口对lcd1602显示，一般都是通过8端口显示的，上传的这个是ise里所建立的工程-On the use of the 4-port lcd1602 display, usually by 8-port display the uploaded this is ise in the established engineering
TechXclusives-MovingDataAcrossAsynchronousClockBo
- Xilinx FPGA moving data across asynchronous clock boundaries
UART_ise7_bak
- 用FPGA 实现全双工异步串口（UART），与PC 机通信。1 位起始位；8 位数据位；一个停止位；无校验位；波特率为2400、4800、9600、11520 任选或可变（可用按键控制波特率模式）。-using FPGA full-duplex asynchronous serial port (UART), and PC communication. An initiation; 8 data spaces; One-stop; No Parity; Baud Rate for 2400,48
HDB3bianjiema
- 关于HDB3码的一种新的编解码形式，可以有CPLD实现。
half_clk
- 用Verilog HDL语言实现的二分频，输出频率是输入频率的一半。-Using Verilog HDL language of the two frequency, output frequency is half the input frequency.
actel FPGA JTAG电路 周立功开发
- actel FPGA JTAG电路 周立功开发 ,actel JTAG
PWM-signal-generator
- 设计脉宽调节信号发生电路，利用计数器实现脉宽可调的信号发生电路。-Pulse width adjustment signal circuit design, the use of counters to achieve pulse-width adjustable signal circuits.
DVP3000J
- ET6202驱动数码管显示，每个按键显示一个数字，用AT89S51作MCU-ET6202-driven digital display, each button displays a number for the MCU to use AT89S51