资源列表
dcfifo_design_example
- ALTERA发布的内部FIFO读写示例，很有参考价值，对初学者会有一定的帮助-ALTERA' s internal FIFO read and write examples of great reference value, there will be some help for beginners
PLL_PID
- 以PID控制实现的Phase detector_Loop Filter_VCO-Phase Locked Loop
shi01
- FPGA上机文件一所以在FPGA中采用同 步设计非常重要 MAX+PLUS II可以计算出数据传输需要(fpga Several of the largest chip operating frequency I would be grateful if the output value of counter FFFFC- FE0FF simulation waveform between the print out (only EPF10K70RC240-4 chips, the maximu
Verilog_1Gb_DDR3_G_Die
- ddr3控制器，速率可达1Gbps，语言使用verilog，已经加入tb(ddr3 controller, can be used to ddr3 control,high speed)
CAN_verilog.tar
- CAN 2.0协议控制器，非常全面的控制器Verilog代码，可靠通信，可放心使用。(CAN Bus 2.0 Controller.)
Altshift_tabs_lab0
- programme en vhdl sur fpga
prog_counter_verilog
- veilog下的程序存储器的程序，可以实现存储和进位等功能-veilog under the program memory, can store and carry other functions
add8
- 8位加法器 verilog + test bench-8 bits add
upload
- A major obstacle that stands in the way of efficient test response compaction are the unknown values (x-values) captured by scan cells during testing. If test responses with x-values are compacted, some of the outputs of the compactor may als
tcpudp
- 在niosii环境下，通过建立SPI核来驱动以太网控制器enc28j60，并通过嵌入tcp/ip协议来实现网口通信。-Niosii environment, through the establishment of the SPI core to drive the Ethernet controller enc28j60 embedded tcp/ip protocol to the network port communications.
EDA-fenpinqi
- EDA多级分频器图形设计，频器输入频率为10 MHz,输出频率为1 Hz。分频器顶层图形文件设计、例化模块图形文件设计。 -Multi-level divider graphic design, frequency input frequency of 10 MHz, the output frequency of 1 Hz. Divider top-level design of graphics files, for example, graphics files of the modu
voter
- 用VHDL语言设计三人表决器 新建VHDL设计文件并保存 检查编译 波形仿真 -Design using VHDL language VHDL three new voting system for the design document and save it to check the compiler waveform simulation