资源列表
biyesheji
- 信号发生器的源代码，VHDL实现，带有ASK，FSK等功能-The signal generator source code, VHDL, with features such as ASK, FSK
FPGA_tbench
- 一个actel公司fpga测试台程序，经过编译可以成功运行-A actel company fpga test program can run successfully compiled
djk2
- 一个模仿了CPU运算器的VHDL小程序，纠结了好几天，终于搞明白了希望能榜上点忙-A parody of the VHDL program in the CPU power, tangled for several days, finally figured it out hope standings point busy
3
- 数码管显示，加上计数器，基础的verilog语言-Digital display, plus the counter, based on verilog language
jieshouji
- 无线通信系统中最佳接收机的硬件描述语言，包括匹配滤波器、RAKE接收机的实现。-The realization of the RAKE receiver
LED
- led流水点亮 实现led顺序点亮 程序简单-led water light
test_led
- 数码管点阵实验，在上显示数字0到9，测试点阵的功能。-Digital tube lattice experiment, shown on figure 0-9, test the function of the lattice.
traffic_Light
- 模拟十字路*通灯的VHDL程序，附有用与配合ModelSim的仿真程序。 内容：交通灯设计 （1）A，B方向各有红，黄，绿灯，初始态全为红灯，之后东西方向通车，绿灯灭后，黄灯闪烁，各路口通车时间为30秒，由两个七段数码管计数，当显示时间小于3秒的时候通车方向黄灯闪烁 （2）系统时钟1KHz，黄灯闪烁时钟要求为2Hz，七段码管的时间显示为1Hz脉冲，即1秒递减一次，在显示时间小于3秒时，通车方向的黄灯以2Hz的频率闪烁，系统中加入外部复位信号。 （3）用ModelSim做仿真
LDR
- This a LDR project. -This is a LDR project.
DDS
- 基于verilog的DDS设计验证与仿真源代码，在quartus上实现，下载仿真成功-Based on the the the verilog DDS design verification and simulation of the source code, in quartus download simulation success
fine
- 4选一多路选择器，计算机组成原理实验的一部分，可扩展为8选一。-Choose more than one way to select the computer form the principle part of an experiment, can be extended to 8 election.
EDAshuzishizhong
- EDA秒表的制作及其源代码 有兴趣的 可以-EDA stopwatch production and its source code are interested can look at