资源列表
UART_DPLL
- 通过串口uart rs232控制的全数字锁相环，dpll， 可锁时钟相位-UART CTORLER DPLL MODULE CLK
D-FLIP-FLOP
- ANALYSIS OF D-FLIPFLOPS
miaobiao
- 设计秒表 可以实现计数清零 停止 实现 59分59秒-miaobiao design
poc
- 用VHDL语言讲述输出控制器（POC）的设计，这是大学课程的设计-VHDL language used on the output controller (POC) design, This is the design of university courses
DAC0832
- 介绍了DA的vhdl语言.在quartus环境中-da vhdl
fenpin
- VerilogHDL语言 将40M分频到4M的分频器-VerilogHDL language 40M sub-4M divider
01-halfadd
- 这是一个成功的半加器VHDL源代码，已在DH－33001开发板上调试成功。-This is a successful half-adder VHDL source code, in the DH-33001 development board debugging.
TCM
- Trellis coded modulation(TCM) VHDL code
Introduction-to-VHDL
- It gives VHDL language details
XAPP289
- Common Switch Interface CSIX-L1 Reference Design
IC_Viterbi
- forward error correction
32bit-RISC-CPU-IP
- 使用Verilog语言实现的RISC精简指令集CPU IP核，该CPU具有32位数据宽度，5级流水线结构和指令预判和中断处理功能，适合Verilog语言深入学习者参考。-Using the Verilog language implementation of RISC Reduced Instruction Set CPU IP cores, the CPU has a 32-bit data width, 5-stage pipeline structure and instruction p