资源列表
vhdl
- this files are for the newcomer thoes who want to learn or study FPGA and VHDL
Design-Reuse-Methodology-For-Asic-And-Fpga-Designe
- asic/fpga设计复用技术 Design-Reuse-Methodology-For-Asic-And-Fpga-Designers-Design-Reuse-Methodology-For-Asic-And-Fpga-Designers
SYSTEM-ON-A-CHIP-Verification
- 芯片设计SoC验证书籍 SYSTEM-ON-A-CHIP-Verification-SYSTEM-ON-A-CHIP-Verification
ASIC-SYNOPSYS
- 芯片设计综合经典书籍 design compiler primetime-asic synthesys
LIP6431CORE_NTSC_Video_Decoder
- NTSC Video Decoder Verilog Source code
LIP6201CORE_mp3
- MPEG3 MP3 Player VHDL source code-MPEG3 MP3 Player VHDL source code
LIP6111CORE_ide_dvd
- IDE DVD Verilog Code
odd_division_wushihai
- 对于实现占空比为50 的N倍奇数分频，首先进行上升沿触发进行模N计数，计数到某一个值n时输出时钟进行翻转，然后再计数（N-1）/2次，再次进行翻转得到一个占空比非50 奇数n分频时钟。同理，同时进行下降沿触发的模N计数，等计数到n时，输出时钟进行翻转，同样再计数（N-1）/2次，输出时钟再次翻转生成占空比非50 的奇数n分频时钟。两个占空比非50 的n分频时钟进行相或运算，即得到占空比为50 的奇数N分频时钟。verilog HDL实现-For achieving a 50 duty cyc
ledwater
- Spartan 3E开发板上实现的流水灯功能-Spartan 3E development board to achieve the water light function
leijiaqi
- 累加器 的VHDL语言源程序~-Accumulator accumulator VHDL language source ~
FPGA
- FPGA最小系统板设计 内容较详尽 给喜欢FPGA的朋友们一点帮助-Minimum System FPGA board design elements like a more detailed FPGA friends to a little help
dds
- DDS技术基于FPGA的应用 dds正弦波发生器 内含源文件~-DDS technology is based on the application of FPGA source files containing the sine wave generator dds ~