资源列表
vhdl1
- vhdl program for 4 bit ripple carry adder using logic gates
vhdl
- vhdl program for d -flipflop with asynchronous reset
VHDLsimCMSG
- a vhdl guide to solve all queries related to vhdl programming
vhdlsample
- vhdl program for bcd conter to 7 segment display
typegame_7-26_final
- 五个字母在屏幕上下落，击中即消并更新字母，实现打字游戏-VHDL code for typegame-- when you press the right key ,than the letter on the screen will update.
123
- 运用VHDL语言，使用FPGA技术，实现四相步进电机的细分步进控制驱动，让电机运行更加稳定，可以实现横转矩。-Using VHDL language, using the FPGA technology, four-phase stepper motor driver stepper control, so that motor run more stable, horizontal torque can be achieved
fff
- 基于软件无线电数传电台的FPGA实现 -Based on software radio data transmitter FPGA Implementation
LIP1215CORE_clkdll
- Clock DLL Block verilog source code
LIP6311CORE_LCD_Interface
- LCD Interface Verilog source code
LIP4101CORE_uart
- UART Verilog sourc code
LIP4331CORE_PCI
- PCI Peripherial Communication Interface BUS Verilog sourc code
LIP4301CORE_PCI
- PCI Verilog source code