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  1. zidongshouhuojisheji

    1下载:
  2. 本文采用Verilog HDL描述语言实现自动售货机系统的销售动作,用有限状态机进行系统状态描述,自动售货机通电复位时,自动进入系统初始状态,本文设计的自动售货机控制系统主要可以实现投币处理、计算投币总额、输出商品,输出找零、余额计算并显示等功能。-This verilog hdl describe language used for automatic machines system of action, with a limited system of state, state, the v
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-04-07
    • 文件大小:33.78kb
    • 提供者:高菲悦
  1. crossnoise-R5

    0下载:
  2. In recent years, due to rapid advances in VLSI manufacturing technology capable of packing more and more devices and wires on a chip, crosstalk has emerged as a serious problem affecting circuit reliability. Even though FPGAs are more immune
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-03-28
    • 文件大小:595.39kb
    • 提供者:sia
  1. crossroute-R4

    0下载:
  2. As integrated circuits are migrated to more advanced technologies, it has become clear that crosstalk is an important physical phenomenon that must be taken into account. Crosstalk has primarily been a concern for ASICs, multi-chip modules, and
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-04-02
    • 文件大小:194.75kb
    • 提供者:sia
  1. parallel_CRC_code

    0下载:
  2. CRC Generation can be done by using PARALLELISM. Efficient method to calculate CRC in less time. By using more hardware for parallel CRC and obtaining more latency and throughput.
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-04-10
    • 文件大小:1.21kb
    • 提供者:Sankar MK
  1. FIFO_Executed

    0下载:
  2. The baove code is Firstb In First Out
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-04-02
    • 文件大小:285.3kb
    • 提供者:Syed Shafi
  1. Multiple_Bit_Adder

    0下载:
  2. The above Code is the executed output for Multiple Bit Adder
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-04-08
    • 文件大小:411.67kb
    • 提供者:Syed Shafi
  1. Parity_Gen_Source

    0下载:
  2. The Included files are the executed Output files of Parity Generator Ciruit
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-04-03
    • 文件大小:319.3kb
    • 提供者:Syed Shafi
  1. RAM

    0下载:
  2. The files attached include the excuted output files for the access of Random Access Memeory
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-04-04
    • 文件大小:250.77kb
    • 提供者:Syed Shafi
  1. Pulse_Generator

    0下载:
  2. The files included are the executed code output for Pulse Generated Circuit
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-04-07
    • 文件大小:268.8kb
    • 提供者:Syed Shafi
  1. Pseudo_Random_Num_Generator

    0下载:
  2. The file included is the source code for Pseudo Random Generator
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-03-29
    • 文件大小:407.5kb
    • 提供者:Syed Shafi
  1. VHDL_Limaye

    0下载:
  2. THIS ONE OF THE VERY GOOD VHDL BOOK-THIS IS ONE OF THE VERY GOOD VHDL BOOK
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-04-06
    • 文件大小:211.63kb
    • 提供者:SUSHANTA
  1. ad0809

    0下载:
  2. 对ad0809的控制代码- ad0809control
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-04-03
    • 文件大小:1.05kb
    • 提供者:邱生贵
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