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  1. 03-NEC_2003_C

    0下载:
  2. 移相信号发生器(2003年C题),verilog源程序,-Phase shift generator Problem C (2003), Verilog source code,
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-04-16
    • 文件大小:321.71kb
    • 提供者:艾米丽
  1. 04-NEC_2003_C

    0下载:
  2. 数字相位测量仪(2003年C题),verilog源程序-digital phase meter Problem C (2003), Verilog source code
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-05-10
    • 文件大小:1.96mb
    • 提供者:艾米丽
  1. 05-NEC_2003_D

    0下载:
  2. 简易逻辑分析仪(2003年D题),verilog源程序-Simple logic analyzer (, 2003 D), Verilog source code
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-04-17
    • 文件大小:407.84kb
    • 提供者:艾米丽
  1. 06-NEC_2005_A

    0下载:
  2. 06-正弦信号发生器(2005年A题),verilog源程序-06- sinusoidal signal generator (2005 A question), Verilog source code
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-04-08
    • 文件大小:706.66kb
    • 提供者:艾米丽
  1. alarm

    0下载:
  2. The red arrow showed the output became 8 when the measured temperature changed to 11°C. As shown by black arrow, the maximum output was 28. The program was run according to the proposed method.
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-04-05
    • 文件大小:99.43kb
    • 提供者:jayjay
  1. comp

    0下载:
  2. The red arrow showed the output became 8 when the measured temperature changed to 11°C. As shown by black arrow, the maximum output was 28. The program was run according to the proposed method.
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-04-04
    • 文件大小:111.97kb
    • 提供者:jayjay
  1. 8.3-LCD

    0下载:
  2. FPGA驱动LCD显示中文字符程序及状态机的使用-FPGA to drive the LCD display Chinese characters procedures and the use of the state machine
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-04-02
    • 文件大小:4.8kb
    • 提供者:林高办
  1. curtain

    0下载:
  2. The red arrow showed the output became 8 when the measured temperature changed to 11°C. As shown by black arrow, the maximum output was 28. The program was run according to the proposed method.
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-03-30
    • 文件大小:112.49kb
    • 提供者:jayjay
  1. lighting

    0下载:
  2. The red arrow showed the output became 8 when the measured temperature changed to 11°C. As shown by black arrow, the maximum output was 28. The program was run according to the proposed method.
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-04-06
    • 文件大小:89.3kb
    • 提供者:jayjay
  1. modulated_gen

    0下载:
  2. The red arrow showed the output became 8 when the measured temperature changed to 11°C. As shown by black arrow, the maximum output was 28. The program was run according to the proposed method.
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-04-17
    • 文件大小:182.62kb
    • 提供者:jayjay
  1. RD1055_rev01.3

    0下载:
  2. NAND Flash Controller Reference Design RD10- NAND Flash Controller Reference Design RD1055
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-04-08
    • 文件大小:583.51kb
    • 提供者:akjfklaskdfj
  1. NAND_Flash_Interface_DF

    1下载:
  2. actel NAND Flash Interface Design Example
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-05-12
    • 文件大小:2.48mb
    • 提供者:akjfklaskdfj
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