资源列表
Example-b3-1
- 每个工程示例都包括了该工程的项目文件、源文件、报告文件和生成结果等文件，读者可以用Quartus II或相应的软件直接打开。设计源文件根据设计输入类型分为源代码或原理图等。-Each project examples include the project files of the project, source files, report files and generate the results files, the reader can use Quartus II or the sof
Alteradesigndocument
- 本实验程序每个工程示例都包括了该工程的项目文件、源文件、报告文件和生成结果等文件，读者可以用Quartus II或相应的软件直接打开。设计源文件根据设计输入类型分为源代码或原理图等。-The experimental procedure for each project examples include the works of the project file, source documents, reports and other documents file and generate th
FPGAtestpapers
- fpga 笔试题很全网上整理的，希望对大家有所帮助-fpga document is full on-line order of questions, we want to help
symbolsandnumericaldecomposition
- Verilog 语言，符号与数值的分解电路-verilog for symbols and numerical decomposition
VHDLnew
- vhdl book by douglas berry
ampliFM100W
- 100w Amplifier very powerful
crc_testbench
- 此为crc测试台文件。主要环境是modelsim。适用于初学者-This is the crc test bench file. Main environment is modelsim. Apply to beginners
eth_crc
- crc校验码Verilog 程序。此为4位并行crc——32校验。-crc checksum Verilog program. This is a 4-bit parallel crc- 32 check.
EPM570
- 这是ATLREA的EPM570的一个144管脚CPLD的最小系统图，对于设计CPLD的板子有作用-This is the EPM570 ATLREA a minimum of 144 pin CPLD system diagram, for the design of the board has the role of CPLD
lcd_fpga
- 在NIOSII环境中应用DE0硬件平台，实现字符在LCD上的显示以及七段译码的字符显示。-Application DE0 NIOSII environment in hardware platform, achieving in the LCD display on the character and the character seven-segment display decoder
clk_counter
- 计数器，可以通过数码管显示数字，包括了分频器，进制设定-clk_counter
Xilinx_DCM
- 基于ise 10.0来实现Xilinx的时钟设计和管理-Xilinx dcm digital clock manager