资源列表
ALTERA_FPGA_SDRAM
- 使用ALTERA的FPGA控制SDRAM的verilog程序-Use ALTERA s FPGA to control SDRAM s verilog program
ROM
- 使用verilog语言实现对altera下cycloneII系列FPGA的片上ROM的创建，读写，调用IP核-Use verilog language to achieve altera under the cycloneII series FPGA on-chip ROM to create, read and write, call IP core
spi_master
- 使用verilog语言实现FPGA下的SPI的主机模式，波特率为晶振时钟的五分之一，发送稳定-Using verilog language to achieve the SPI under the host mode, the baud rate is one-fifth of the crystal clock, send stable
18.UART
- 使用verilog语言实现FPGA上的串口程序编写，可实现9600波特率下的收发功能，且占用逻辑单元较少-The use of verilog language FPGA on the serial program to achieve, can achieve 9600 baud rate transceiver function, and occupy less logical unit
spi_slave
- FPGA实现SPI接口的从机功能，接收和发送全双工运行，接收到的数据以八位LED灯显示-FPGA to achieve the SPI interface the machine function, receive and send full-duplex operation, the received data to eight LED lights
PCIe_Lab
- PCIe lab据说是研讨会的资料，大家有需要的可以-PCIe lab It is said that it is a seminar information, have a try if you need
sineWaveGenerator
- FPGA生成高质量400Hz正弦信号的代码，可调节信号频率、初相位及信号质量-FPGA generated code 400Hz sinusoidal signal quality, signal frequency can be adjusted, and the initial phase of signal quality
pdm
- 适用于endat2.2协议的线缆延迟补偿模块，用于修正因线缆延迟导致的时序错位-Endat2.2 protocol suitable for the cable delay compensation means for correcting the timing misalignment due to a delay caused by cables
endatreduced
- endat2.2协议对应的驱动模块代码，适用于开发面向海德汉编码器反馈环控制模块-endat2.2 driver module corresponding to the protocol codes, for developing suitable feedback loop Heidenhain encoder control module
Uart_Randy
- this s the uart source code and document
UpdateApp1.2
- 这是FPGA的升级程序，C#发送bin文件给FX3，然后FX3再把数据通过SPI通信发送给FPGA-This upgrade program the FPGA, C# FX3 sent to the bin, and then FX3 data to the FPGA via SPI communications
sources_1
- 使用 wtfa pfa方法 混合基搭建 600点fft verilog -Wtfa pfa method using a mixed group to build a 600-point fft verilog