资源列表
synplify-ISE-ModelSim
- 关于FPGA的仿真文档，使用synoplify，ise和modelsim三者联合仿真，适合初学者入门-FPGA on the simulation of the document, the use of synoplify, ise and modelsim co-simulation, suitable for beginners entry
lpc
- INTEL的LPC总线-INTEL s LPC bus............................................................................
aes-128_pipelined_encryption
- AES 加密算法 基于流水线设计 成熟IP core-AES encryption algorithm based on pipeline design mature IP core
VGA
- VGA显示彩条，作为调试VGA接口的小程序。完整工程奉上。-VGA display color bars as small debugging VGA connector. Complete engineering offer.
FPGA_exp2
- 调节数码管显示的文件，适用于CYCLONE II 开发板， 用VHDL语言编写，非常适合移植进数字钟中以实现调节时间的功能。 多模块设计简单明了。-Adjust digital display files for CYCLONE II development board, using VHDL language, it is very suitable for transplantation into digital clock to realize the function of regula
LSD
- 用VHDL语言写的流水灯，适用于最新的CYCLONE V 实验环境，工程文件附上，管脚分配已经完成。需要实验书可联系2942551049@qq.com-VHDL language used to write the water lights for the latest CYCLONE V test environment, engineering documents attached, pin assignment has been completed. Experiments need to
CLOCK
- 实现电子钟，连接数码管显示，手写原创，使用CYCLONE V ，已经验证成功，附上工程文件-Implement electronic clock, use CYCLONE V, has been successfully verified, attach the project file
tinycpufiles
- TinyCPU源码,使用Verilog编写的资源占用极少的CPU。Quartus工程，可跑在Altera MAXII CPLD上,也很方便移植到其他FPGA上。CPU使用200个逻辑单元，外设(SPI,LCD等)使用180个逻辑单元。 内含汇编编译器源码(VC2008)，可编译CPU对应的汇编文件。-The sourcecode of TinyCPU, which only consumed very few logical cells, written by Verilog. It is
SPI
- 通过SPI协议使用Verilog显示流水灯。-Verilog is used to display the flow lamp via the SPI protocol.
fm
- FM调频的FPGA程序，用ALTERA的FPGA实现-FM altera fpga veriloghdl
11_ddr3_test
- ddr3的操作程序，用Veriloghdl写的FPGA程序-ddr3 veirloghdl operater xinlinx FPGA
21_flash_ddr_lcd
- flash与DDR3的程序，verilogHDL语言描述的程序-flash and ddr3 verilogHDL soft