资源列表
singnt
- 基于verilog的正弦发生器,可以产生正弦信号-Based verilog sine generator，Can produce a sinusoidal signal
verilog经典实例
- 讲述了135个有关verilog的经典例程。帮助您快速掌握verilog这门语言。
DDS
- 用FPGA实现DDS，代码测试正确，可用于初学者学习使用-FPGA with DDS, code testing is correct, can be used for beginners to learn to use
design
- 状态机描述风格，具有工程价值的状态机结构 源自华为内部-State machine descr iption style, with the value of the state machine structure- Huawei internal
cic
- 无线通信中的DDS原理，讲解了FPGA实现数字频率合成器-Wireless communication in the DDS principle, to explain the FPGA to achieve digital frequency synthesizer
decode
- 用Verilog实现汉明码的解码，经测试可以正常使用，且代码简介-Verilog with Hamming code to achieve the decoding, the test can be used normally, and the code
decode
- 用Verilog实现汉明码编码，经测试可正确使用，代码简洁-Verilog with Hamming code encoding, the test can be used correctly, the code is simple
aurora_IP
- Aurora协议是一款高带宽、低成本、可扩展、框架简洁、适合点对点串行数据传输的协议。-Aurora protocol is a high-bandwidth, low-cost, scalable, simple framework for point to point serial data transfer protocol.
16_sd_test
- SD卡相关FPGA程序VHDL源代码，可直接用！用ISE打开！-Sd card related FPGA program VHDL source code, can use directly!Using ISE open!
08_eeprom_test
- eeprom相关FPGA程序VHDL源代码，可直接用！用ISE打开！-eeprom related FPGA program VHDL source code, can use directly!Using ISE open!
30_ad706_test
- ad706相关FPGA程序VHDL源代码，可直接用！用ISE打开！-Ad706 related FPGA program VHDL source code, can use directly!
29_ad9226_test
- ad9226相关FPGA程序VHDL源代码，可直接用！-Ad9226 related FPGA program VHDL source code, can use directly!