资源列表
16bitADC
- verilog实现的16位模数转换器参考源代码-verilog to achieve 16-bit ADC reference source code
bin_bcd
- verilog实现的而进制转BCD码的源码-verilog implementation of the binary code of the source switch BCD
PCK_CRC16_D1
- CRC源代码，VHDL文件，可供参考，16位的-CRC source code, VHDL files, for reference, 16-bit
div_n
- verilog占空比50奇偶任意 奇偶任意分频器！包括测试代码-verilog random duty cycle of 50 odd parity arbitrary divider! Including test code
uart
- verilog实现的按键控制的串口简单收发通信-verilog implementation simple keypad control, serial communication transceiver
323
- VHDL方面的资料，有助于对VHDL有一个了解-VHDL information, facilitate an understanding of VHDL
SINGT
- 简单的正弦信号发生器。利用lpm功能模块设计。-Simple sinusoidal signal generator. Design of functional modules using lpm.
qj
- 全加器。使用Vhdl语言实现数字电路全加器功能，算法比较简单，供初学者参考。-Full adder. Digital circuits using Vhdl language full adder function, the algorithm is relatively simple for advanced users.
CLOCK3
- 时钟与报警器源程序，功能强大，资源少。操作简便-Clock and alarm source, powerful, less resources. Simple
vhdl
- 3分频 器，LED分位译码电路，交通控制器，序列检测器-four programs based on vhdl
FPGAPS2interface
- FPGA控制的PS/2接口 内容是基于状态机的FPGA控制的PS/2接口 大家看看 不好的提出建议-FPGA-PS2-interface