资源列表
sevensegment
- seven segment simple coding
halfadder
- single bit half adder
fulladder
- single bit full adder
counter4bit
- 4 bit fpga code for beginner
counter
- this the 1 bit counter clock where the counter increase by 1 on rising edge clock-this is the 1 bit counter clock where the counter increase by 1 on rising edge clock
I2Csrc
- source I2c controller WB uC bus plus alternative controlling- verilog code
Vga
- VHDL code to digitally control the interface with a VGA display. Code is technologically independent and can be prototyped in any programmable device or ASIC.
rzn725SDH
- 一个关于SDH中TU-12解帧的VHDL代码-On the SDH in a solution of TU-12 frame VHDL code for
FPGA_Based_Multi-channels_Serial_ADC_controller.ra
- 采用FPGA控制ADS7844进行模数转换。ADS7844 是Burr_Brown公司推出的一种高性能、宽电压、低功耗的12 b串行数模转换器。它有8个模拟输入端，可用软件编程为8通道单端输入A／D转换器或4通道差分输入A／D转换器，其转换率高达200 kHz，而线性误差和差分误差最大仅为±1 LSB。-Using FPGA control ADS7844 analog to digital conversion. ADS7844 is a Burr_Brown the company intr
fenpinqi
- 经典的分频器程序设计，分辨对偶数倍分频和奇数倍分频进行了EDA的程序编写，通过这两个程序，可写出所有的分频器设计-Classic divider programming, identify multiple points on the dual-frequency and odd multiples of the sub-frequency EDA programming carried out by these two programs can be designed to write all
QuartusII_error_Analysis
- altera fpga编程过程中常出现一些错误及其消除方式，属于集体智慧的结晶-altera fpga programming mistakes often occur during its elimination method, belonging to the crystallization of collective wisdom
sopc_timer
- sopc的一个典型应用，使用的部件为niosII软核中的timer定时器，内容详细，包括所有的源代码。-sopc a typical application, the use of soft-core components of niosII timer in the timer and detailed, including all the source code.