资源列表
async_fifo
- verilog HDL写的异步fifo代码及测试平台，直接可用，可生成RTL代码-asynchronous fifo write verilog HDL code and test platform, directly available, can generate RTL code for
lattice_practical_power
- PRACTICAL LOW POWER CPLD DESIGN Common (And Not-So-Common) Design Techniques That Can Help Reduce Power Consumption
FPGA51he
- 这是一个51单片机嵌入在FPGA中的ip核，这个核它完全兼容我们普通的8051单片机，也就是说程序在这个上面一样可以跑起来-This is a 51 microcontroller embedded in the FPGA in the ip core, the core is fully compatible with our ordinary 8051, that the program can run up the same as above
fira
- 这是一个用FPGA中DSP Bulider做的一个FIR滤波器，很好使用，我已经测试过了-This is an FPGA, DSP Bulider used to do a FIR filter, a very good use, I have tested the
shiboqi(chugao)
- 这个方案是在FPGA中嵌入51单片机IP核，通过51单片机的控制来很方便的实现对数字存储示波器的显示和控制！是我国赛训练的一个题目！-This program is embedded in the FPGA microcontroller IP core 51 through 51 SCM control to easily realize the digital storage oscilloscope display and control! The training of our race
Frequencydivider
- A frequency divider is an electronic circuit that takes an input signal with a frequency, fin, and generates an output signal with a frequency:
DDS
- 同时用verilog 语言编写dds原代码用于生成正余弦波，并在FPGA平台进行验证-described dds direct digital frequency synthesis of the basic tenets addition to the use of verilog prepared dds source used to produce sine, and FPGA development platform for verification
uart_vhdl
- 异步通信接口包括测试文件，有三个模块组成-Asynchronous communication interfaces, including the test file, there are three modules
SotaylaptrinhVHDl
- vhdl hand book. vietnamese language
Acr67.tmp
- 教你如何使用modelsim 非常好一个的教程-Teach you how to use the modelsim a very good tutorial
uart-vhdl-testbench
- simple uart vhdl behavioural model (package) vhdl testbench example
90205E3Cd01
- Verilog Design in the Real World