资源列表
verilog
- Verilog HDL程序设计教程常用verilog模块，特别好的学习资料-" Verilog HDL Programming Guide" verilog modules used, in particular, good learning materials
DDS
- FPGA实现直接数字频率合成（DDS），使用EP1C3T144C8通过调试-Cyclone,aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa
presentation_pfe_v3.6.ppt
- Jtag communication design with VHDL scr ipt
FPGArealiztionofdigitalsignalprocessing
- 数字信号处理FPGA实现 实用程序和文件,有sine.exe ---输入宽度。输出对应的正弦波表 mif文件 csd.exe --- 寻找整数和分数的标准有符号数字量（canonical signed digit ，CSD）表达式程序 fpinv.exe --- 倒数计算浮点数表的程序 dagen.exe ---分布式算法文件生成HDL" onclick="tagshow(event)" class="t_tag">VHD
asynfifo
- 异步fifo，用Verilog编写，包含testbench，已经通过调试，需要的下载-Asynchronous fifo, to prepare to use Verilog, including testbench, debugging has been passed, the need to download
dpram2
- vhdl写的双口ram，真正实现双口通信-I write vhdl dual ram, true dual-port communication
mapped_and_demapper
- Mapper and Demapper in vhdl code
200M_DA_AD
- 自己编的，用FPGA实现软件DDS调幅。编程语言是VHDL。拿出来相互学习一下。-Own, and with FPGA AM DDS software. Programming language is VHDL. Look out to learn from each other.
dds
- fpga利用dds原理，产生正弦波，简单实用，成本低-fpga using dds principle, have a sine wave
fft2
- 基于FPGA的FFT设计，非常经典，能使用-The FFT-based FPGA design, very classic, can use
cfft
- 基于FPGA的快速傅里叶算法设计，VHDL语言写的，编译可通过-FPGA-based fast Fourier algorithm design, VHDL language, the compiler can
BCD
- vhdl写的十进制转BCD的源代码-vhdl decimal to BCD written the source code~~~~~~~~~~~~~~~~~