资源列表
DDS
- 基于FPGA的直接数字信号合成器的代码 仅供大家参考-direct digital frequency sythesis based on FPGA
div-8.5
- 文件格式：VHDL语言。是自己根据具体需要编写的，并通过时序仿真完全正确。改程序是可以直接解压，然后通过Quartus II打开，编译和仿真。十分方便，好用！-File Format: VHDL language. According to the specific needs of their own prepared, and timing simulation entirely correct. Procedures can be directly diverted to extract,
FPGAboxin
- FPGA实现波形产生模块能产生正弦，方波，锯齿，三角波的产生，频率可调-fpga
avr_core2_VHDL
- avr_core2_VHDL source-avr_core2_VHDL source
arithmetic
- 在Verilog环境下实现简单的数学逻辑运算从而更好的了解 VHDL的编程风格-arithmetic
vidiocpt
- 本代码为富士通MV86S02的CMOS图像传感器的VHDL驱动代码-The code for Fujitsu MV86S02 the CMOS image sensor-driven VHDL code
ad9777_ini
- Verilog编写的AD9777初始化代码-Verilog code to initialize the preparation of the AD9777
AD_ctrl
- 用VHDL编程实现的基于FPGA的adc0809和ad1674的控制模块，做数据采集的朋友可以看一下。-VHDL Programming with FPGA-based control adc0809 and ad1674 modules, data acquisition so friends can see.
clock
- 以前做的EDA课程设计，CLOCK,可设置时间的,6位数码管显示-Done before the EDA curriculum design, CLOCK, may set the time, digital tube display 6
request_arbiter
- // Inputs --- // DMACSREQ_i -- The 16-bit signal which stores the single request of all the 16 devices // DMACBREQ_i -- The 16-bit signal which stores the burst request of all the 16 devices // hclk_i -- Clock signal // hresetn_i -- Active l
Traffic_llight_controller
- Consider the following variation on the traffic light controller problem. A North-South road intersects an East-West road. In addition to the Red/Yellow/Green traffic lights, the N-S road has green left-turn arrows. The arrows work as follows. Wit
digital_lock
- Verilog code for digital combinational lock //BCAC – Unlock sequence //wrong sequence –alaram goes on and goes off only after pressin another 4 wrong buttons. //once the lock is open ,we can close the lock by pressin any key //From any state