资源列表
HDB3_coder
- 实现了将64K低速NRZ码复接成2.048M高速HDB3码及其解复接过程，同时还用同步状态机剔除假同步和假失步的状态 -Achieved the 64K low-speed NRZ code 2.048M into high-speed multiplexing and demultiplexing HDB3 code then the process also removed using false synchronous state machine synchronization and f
FPGA_SOPC
- fpga的基础实验，SOPC的入门实验初学者-fpga experimental basis, SOPC beginners entry experiment
topmodule3_comments
- it is a 1/2 k=3 viterbi deocder code written in VHDL.
FPGA_PCI_DATA
- 一个基于FPGA的PCI数据发送程序，实现从计算机通过PCI9054向FPGA发送数据功能。开发语言verilog,开发环境quartus-FPGA-based PCI data distribution process, from the computer through the PCI9054 functions to send data to the FPGA. The development of language verilog, development environment qua
LCDDriver-ML505-EDK10-1
- Sourcecode on MicroBlade processor for LCD driver on ML505 Xilinx Board
5Divide
- 用Verilog HDL语言写的标准的5分频程序，可以立即使用-Verilog HDL language used to write the standard procedure of 5 min frequency, you can immediately use
pinlvji
- 等精度频率计设计，很好的源代码，附上工程文件，在quartus5.0以上版本即可运行。-Design accuracy, such as frequency meter, a good source code, attached to the project document, in the above quartus5.0 to run.
fpga.doc
- this gives detail about FPGA kid you can get fpga kid for learning purpose
EDA_project
- 基于Verilog和VHDL的DDS程序 基于VHDL的8位十进制频率计 -Verilog and VHDL based on the DDS process VHDL-based 8-bit decimal Cymometer
digital_clock_design
- 利用VHDL语言，逻辑器件设计CPLD，实现数字钟-Using VHDL language, design of logic devices CPLD, digital clock
61003107
- 公 共 电 话 通 话 计 费 系 统 在本课程中所选择的课题是用Verilog HDL实现的公共电话。该公共电话所实现的功能有打电话、修改密码。 公共电话共包括以下几个状态：挂机、待机、身份确认、修改密码、通话等五个状态。-The pay phone converses to charge system In this course the topic chosen is use Verilog HDL carry out of pay phone.The function carri
DE2_LCM_TV_NTSC
- DE2上的基于FPGA视频开发资料第二部分-DE2 video