资源列表
PLD
- vhdl语言实现cpld功能，本程序包括全加器，触发器，交通灯程序，适用maxII软件调试。-include full_adder,plus,traffic
lcd_test
- 基于FPGA的LCD1602a显示.在液晶屏上显示英文字符“My rongrong”-FPGA-based display LCD1602a. In LCD display English characters "My rongrong"
seqdett
- 用于序列检测的一个模块 -Sequence detector modules
48led
- 此软件用的是QuartusII 5.1的环境编写的CPLD内的程序，CPLD用的是EPM7128，实现的功能是对计算机的ISA总线读写操作，计算机通过ISA总线，再通过CPLD，来控制LED的亮和灭-This software is used in the preparation of QuartusII 5.1 environment within the CPLD procedures, CPLD using EPM7128, the function of the realization
1508
- 是CPLD内的程序 控制6个电机，同时还用液晶显示的图的工程中采用了cpld-CPLD program is within the six motors, but also plans to use liquid crystal display used in the project cpld
SEVEN_SEG
- vhdl seven segment key input test progra,
w1231312312
- 分频器，非常有用，已经在FPGA上测试成功，对大家学习很有帮助。-Prescaler, very useful, has been tested successfully in the FPGA, very helpful for all of us.
frequency
- 用verilgHDL语言编写的数字频率计代码，并在QUARTUS下实现-Language used verilgHDL Digital Cymometer code, and under QUARTUS
shiyan10
- VHDL实用的时钟程序，已经通过实验，大家可以下载使用-VHDL Clock practical procedures are experimental, you can download to use
VHDL
- 包括用用VHDL语言编写的DDS,FIFO,交通控制灯，数字电压计，信号发生器的源码，希望能帮到大家-Including the use of VHDL language with the DDS, FIFO, traffic control lights, digital voltage, the signal generator of the source, I hope to help you
Verilog_HDL_Exercises
- 提供了verilog编程的例子，并进行了详细的分析，适合初学者-Verilog provides programming examples, and has done a detailed analysis, suitable for beginners
tes_amp_80_0314
- 基于dsp builder的数字下变频器，IP核做的-digital down converter,degigned in matlab