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资源列表
FPGAbasedschematicdiagramofthephasemeasurement
- 基于FPGA的相位测量原理图,完全用原理图的方式对相位差进行测量-FPGA-based schematic diagram of the phase measurement, complete with schematic diagram of the measurement on the phase difference
CPU
- 利用vhdl模拟实现CPU的功能，实现其中的加减乘除等多种运算-CPU utilization of vhdl simulation of the realization of the function, the realization of which, such as addition and subtraction, multiplication and division multiple computing
XYJ
- 洗衣机控制程序，只需在QUARTUS中编译即可使用-washing machine controler
VHDLcodingStyle
- VHDL设计编码规范 VHDL设计编码规范-VHDL Design Coding Design Coding VHDL specification norms
VHDLmultiplier
- 利用VHDL设计乘法器4乘4 利用VHDL设计乘法器4乘4-VHDL design using 4 × 4 multiplier
VHDL
- VHDL hardware descr iption language
fifo
- first in first out VHDL code
quartus
- quartus中常见错误的解析以及解决办法，主要是VHDL也verilog HDL-Common Errors in quartus and the analytic solutions is mainly VHDL also verilog HDL
TheDesignofFIRFilterBasedonFPGA
- 从分析FIR 数字滤波器的原理和设计方法入手,主要针对基于FPGA 实现数字滤波器乘法器的算法进行了比较研究,并通过一个8 阶FIR 低通滤波器的具体设计,简要分析比较了几种算法的优越性和缺点,从而充分发掘和利用FPGA 的高速特性。-From the analysis of FIR digital filter design theory and approach, mainly based on the realization of digital filter FPGA multiplie
code
- modelsim下的60进制计数器源码和测试激励文件-modelsim M counter 60 under the source file and test incentives
ucGUI_3.24_NiosII_JimYang
- 嵌入式图形界面开发(NIOSII),uc/GUI 3.24 porting for NiosII 5.1 (SED1335 Controller)-Embedded GUI development (NIOSII), uc/GUI 3.24 porting for NiosII 5.1 (SED1335 Controller)
20080402090643447
- 一篇关于利用VHDL语言设计的南北交通灯-VHDL language on the use of a north-south traffic light design