资源列表
SSRAM_by_Verilog
- ssram读写接口设计的详细资料，具有指导价值。包括了主要的读写源代码和时序图。-Details interface design of reading and writing of ssram，it have guidance value.Including the main source code to read and write and sequence diagram.
SSRAM_250M
- 本人编写的SSRAM高速读写工程，工程中包含了NIOS软核，利用Quartus的TimeQuest工具进行了时序约束，上班调试最高读写速率可达250MHz。-I write the SSRAM high-speed, speaking, reading and writing, engineering includes NIOS soft core, timing constraint is studied by using Quartus TimeQuest tools, work to de
DDR2_VERILOG
- 基于FPGA的DDR2_SDRAM的实现Verilog代码，比较实用，经过仿真验证。-Based on the FPGA implementation of DDR2_SDRAM Verilog code, more practical, proven by simulation.
verilog_EXAMPLE_100-
- 产用的Verilog语言设计实例，适合初学者，代码通过验证。包含PCI、i2c等-Production design example Verilog language, suitable for beginners, through the verification code.Contains the PCI, i2c, etc
kcpsm3
- main VHDL entity for PicoBlaze chip control
CRC_test
- 基于verilog编写的CRC校验程序，采用LFSR电路实现。-CRC verilog
RLS-Algorithm
- I am giving new files related to RLS algorithm
dianziqin2--lcd
- 基于Altera公司的开发板DE2--EP2C35F672C6，制作的电子琴，实现do、re、mi、fa、sol、la、xi、do八个音调，并可选择手动或自动播放，其中手动播放可实现存储与回放。并可实现液晶屏对音符的显示。-Development board based on Altera' s DE2- EP2C35F672C6, making organ, realize do, re, mi, fa, sol, la, xi, do eight tones, and can choo
DE0_NANO_VGA
- ntity DE0_NANO is Port ( CLOCK_50 : in STD_LOGIC --//////////// LED ////////// LED : out STD_LOGIC_VECTOR(7 DOWNTO 0) -- --//////////// KEY ////////// KEY : in STD_LOGIC_VECTOR(1 DOWNTO 0) -- --//////////// SW ////////// S
decimal_divider_nr_norm
- - non-restoring like divider. As in Paper. -- For normalized numbers -- non-restoring like divider. As in Paper. -- For normalized numbers ---------------------------------------------------------------------------------
sdram_controller
- sdram的控制器代码 sdram的控制器代码 sdram的控制器代码-sdram controller
RGB-color-bar[Verilog]
- 基于FPGA的 VGA彩条试验 Verilog-Verilog VGA color bar test based on FPGA