搜索资源列表
EDA
- 移位相加8位硬件乘法器电路设计,该乘法器是由8位加法器构成的以时序方式设计的8位乘法器。-Add 8-bit hardware multiplier shift circuit design, the multiplier is composed of 8-bit adder to temporal order, 8-bit multiplier design.
BCD_adder_4digit
- 首先将最大四位的整数转换成BCD码,然后用VHDL设计一个4位BCD码加法器,-BCD_adder_4digit
lfsr
- 用LSFR实现计数功能,可以减少对寄存器和少一个加法器,涉及verilog的人来说-Used to achieve LSFR counting functions, can be reduced to a few registers and adders, the people involved in Verilog
adder
- cpld/fpga常用加法器设计的verilog程序-cpld/fpga common adder Verilog design procedures
c15_add
- 精通verilog HDL语言编程源码之1--常用加法器设计-Proficient in programming language source verilog HDL of 1- Common adder design
OPERATION_UNIT
- 本程序为加密芯片内部加密运算单元部分,包括32位减法器、移位寄存器、加/减法器、寄存器等,对密码芯片运算部分设计具有一定指导意义-The procedure for encryption chip unit internal encryption algorithms, including 32-bit subtraction, and shift register, add/subtraction, and register and so on password-chip design has
mybole3
- 对话框和文本,对话框展开和收缩功能,菜单功能,加法器功能。-Dialog box and the text of the dialog box to start and systolic function, menu function, adder function.
4bit_buma_adder
- Verilog作业 :自己写的源码输入,补码输出的,由状态机控制的四位加法器,为保证时序,加法器模块为超前近位加法器,包含测试台,通过 Modelsim 、Synplify仿真。-Verilog operation: the source code to write their own input, complementary code output by the state machine to control the four adder, in order to ensure timing
huibian
- 1、汇编课程设计 2、包括如下:(1)、简单文件管理 (2)、学生成绩管理 (3)、简单加法器 3、文档中附有代码 -1, the compilation of the curriculum design 2, include the following: (1), a simple document management (2), student performance management (3), simple adder 3, a document with th
half_adder
- 实现一位加法器的设计,假设输入参数为A,B,则输出为A,B的和-The realization of an adder design, the assumption that the input parameters for the A, B, the output of A, B and
minicore
- minicore为一个加法器的最小结构,含有移位RAM 和调试的TB 程序等。-minicore for a minimum adder structure, containing translocation TB of RAM and debug procedures.
VHDL
- 1 8位加法器的设计 2 分频电路 3 数字秒表的设计-1 8 adder design of 2-circuit design of 3 digital stopwatch
adder4
- 是用verilog写得加法器以及计数器里面有测试文件(testbench),对于初学者来说这个可以用来参考下-Is written in Verilog adder and counter inside a test file (testbench), for beginners this can be used to reference the next
100vhdl_example
- vhdl语言的100个例子 VHDL语言100例 第1例 带控制端口的加法器 第2例 无控制端口的加法器 第3例 乘法器 第4例 比较器 第5例 二路选择器 第6例 寄存器 第7例 移位寄存器 第8例 综合单元库 第9例 七值逻辑与基本数据类型 第10例 函数 -VHDL language, VHDL language 100 examples of 100 cases of the first one cases of the control p
AddTwoNumber
- VB.NET编程基础练习资料,实现简单的加法器功能,程序简单,易理解.-VB.NET Programming information on the basis of practice, the realization of a simple adder function, the program is simple and easy to understand.
freq
- vhdl语言设计频率计,十进制加法器.运用maxplus2运行,-VHDL language design frequency, the decimal adder. maxplus2 application running,
fir_parall
- 基于verilog的fir滤波器设计,用的并行结构。在前面基础上加入四级流水(加法器,并行乘法器,乘法结果相加两级),通过验证。-Verilog-based design of fir filter using the parallel architecture. In front of the basis of adding four water (adder, parallel multiplier, multiply the result of the sum of two), throu
bwcfq
- 纯组合逻辑构成的乘法器虽然工作速度比较快,但过于占用硬件资源,难以实现宽位乘法器,基于PLD器件外接ROM九九表的乘法器则无法构成单片系统,也不实用。这里介绍由八位加法器构成的以时序逻辑方式设计的八位乘法器,具有一定的实用价值,而且由FPGA构成实验系统后,可以很容易的用ASIC大型集成芯片来完成,性价比高,可操作性强。-err
ALU
- ALU加法器的设计,实现带进位的加法运算!-ALU adder design, the realization of the adder into the bit computing!
addr8
- 8位加法器VHDL源程序,实验题能够在EDA开发系统中运行-8-bit adder VHDL source code, experimental questions can be developed in the EDA system to run