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本代码功能为实现38/30KHZ红外线接收功能
程序通过quartusII 8.1编译，使用verilog语言编写。
可在彬杰科技*BJTECH公司基于altera epm240的开发板上验证。
（开发板网址http://item.taobao.com/auction/item_detail-0db1-69fe7069aa3ba544abf783bc4427b377.htm）
有需要的朋友可以下载参考-The code functions to achieve 38/30KHZ
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本代码功能为实现接收PS2键盘编码功能。
程序通过quartusII 8.1编译，使用verilog语言编写。
可在彬杰科技*BJTECH公司基于altera epm240的开发板上验证。
（开发板网址http://item.taobao.com/auction/item_detail-0db1-69fe7069aa3ba544abf783bc4427b377.htm）
有需要的朋友可以下载参考-The code functions to achieve the receiver
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本代码功能为实现输入时钟的1.5分频功能。
程序通过quartusII 8.1编译，使用verilog语言编写。
可在彬杰科技*BJTECH公司基于altera epm240的开发板上验证。
（开发板网址http://item.taobao.com/auction/item_detail-0db1-69fe7069aa3ba544abf783bc4427b377.htm）
有需要的朋友可以下载参考-The code functions as the input clock fre
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this pdf file will gives the details of synopsys tool design space and verilog HDL ASIC design based tips.also this pdf is a power point presentation with functional verification tool of synopsys VCS tool.... VERY USEFULL FOR PROFESSORS
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讲述使用modelsim进行验证，使用verilogHDL语言进行建模。其中还包括一个讲述怎样用verilog语言编写测试台的详细文档，对fpga cpld设计的后期验证有很大的帮助。-About the use modelsim for authentication, use verilogHDL language modeling. It also includes a focus on how to use verilog test bench written a detailed doc
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介绍Verilog HDL, 内容包括：Verilog应用，Verilog语言的构成元素，结构级描述及仿真
，行为级描述及仿真，延时的特点及说明
介绍Verilog testbench，激励和控制和描述
结果的产生及验证，任务task及函数function
用户定义的基本单元(primitive)，可综合的Verilog描述风格等-Introduction Verilog HDL, including: Verilog applications, Verilog language
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7:1LVDS编码 为LVDS方面需求的人提供参考设计，很高兴- This VHDL or Verilog source code is intended as a design reference which illustrates how these types of functions can be implemented.
It is the user s responsibility to verify their design for
consistency a
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使用verilog语言实现任意分频的设计，各位verilog学习者或者IC设计验证人员可以参考。-Verilog language use the design of any frequency, you verilog learners or who can refer to IC design verification.
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SPECMAN基本指导，供VERILOG验证工程师使用。-SPECMAN basic guide for verification engineers VERILOG.
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vpi/pli socket example code-co-verification using TCP/IP socket (hardware model : verilog+ vpi as server) (software as a client)
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采用Verilog语言编写实现7段数码管的静态显示，经过CPLD开发板验证，程序正确-Verilog language used to achieve a static 7-segment display, after a CPLD development board verification, the program correctly
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RS232串口通信程序，经过开发板验证，程序正确无误，是采用Verilog语言编写的-RS232 serial communication program, through the development board verification, the program is correct, is written using Verilog
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设计与验证verilog hdl配套光盘-Supporting the design and verification of verilog hdl CD
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It is switch design (RTL) implemented in verilog and have a verification environment in verilog
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It is verification environment made in system verilog for verification of switch
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这个是12位的除法器，进过验证的，verilog程序，应用组合逻辑，欢迎下载-This is 12-bit divider, been to verification, verilog, application logic combinations are welcome to download
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Verilog 设计与验证源码+PDF，经典教程，对与RTL和状态机的理解有很大帮助，适合FPGA开发工程师。-Verilog design and verification source+ PDF, classic tutorial, and state machine understanding of RTL helps a lot, suitable for the FPGA development engineers.
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In the semiconductor and electronic design industry, Verilog is a hardware descr iption language (HDL) used to model electronic systems. Verilog HDL, not to be confused with VHDL (a competing language), is most commonly used in the design, verificati
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IEEE802_16e协议实现的VERILOG代码及MATLAB验证方案。-IEEE802_16e protocol of VERILOG code and MATLAB verification program。
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uart的verilog代码，在赛灵思的spartan 3E上经过验证，电路有一定的质量。-The verilog uart code, in the spirit of the best Spartan 3 E after verification, circuit has certain quality.
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