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csa_verilog_rtl
- CSA加扰算法verilog实现，代码经过fpga验证，可以正确实现该算法。-CSA verilog rtl codeing
ai32-RTL
- verilog code analog output board
light
- 逻辑控制，门级设计RTL描述，用LED显示-Logic control, gate-level RTL design descr iption, with LED display
Freescale
- Freescale moude+飞思卡尔测速程序,PT0脉冲累计,RTL实+=第六讲 功能模块+MC9S12超详细中文资料+XS128_各模块整理资料+飞思卡尔中文资料(Freescale)-ColdFire编程参考手册+手把手教你写S12XS128程序-Freescale moude+ Freescale speed program, PT0 pulse total, RTL real+ = Lecture 6 modules+ MC9S12 ultra-detailed Chinese da
F6_6
- F6: Introduction to RTL Synthesis
PoE_2temac_TOP
- 基于xilinx公司生产的FPGA可编程逻辑芯片的千兆网卡的设计代码。-1000Mhz Ethernet TEMAC xilinx fpga vhdl RTL
coding_and_synthesis_with_verilog
- In the semiconductor and electronic design industry, Verilog is a hardware descr iption language (HDL) used to model electronic systems. Verilog HDL, not to be confused with VHDL (a competing language), is most commonly used in the design, verificati
coding-style
- QA培训资料,一、 RTL CODE 规范-QA training materials, a, RTL CODE specification
ChipScope
- 1学习chipscope的使用方法，并建立一个简单的计数器工程，用chipscope观察计数过程； 2. counter目录里面是chipscope使用在计数器的工程； 3. icon目录 4. ila目录 5. vio目录 6. rtl目录 7. download目录 -1 Learning chipscope to use, and create a simple counter project, with chipscope observe the counti
char_LCD
- 1. 本实例控制开发板上面的LCD的显示； 2. 工程在\project文件夹里面 3. 源文件和管脚分配在\rtl文件夹里面 4. 下载文件在\download文件夹里面,.mcs为PROM模式下载文件,.bit为JTAG调试下载文件-1 The examples above control development board LCD display 2 works in \ project folder inside 3 source file and the pin a
rtl
- 51单片机+RTL8019上网编程指南开发指南 51单片机+RTL8019上网编程指南-Development guidelines--51 SCM+ RTL8019 Internet programming guide
image
- 改程序在pc上实现，是一个用户专用的打印驱动程序，用于将HP-RTL指令嵌入于光栅数据中发送给支持HP-RTL指令的打印机打印图像-THIS function is used to suppot HP-RTL code embeded into raster data.
aFifo.vhd.txt
- Async. FIFO for rtl coding and simulation
TCP
- 单片机控制RTL 8019以太网接口实例，原理图和详细的源代码。-SCM control RTL8019AS Ethernet interface instance, with schematic diagram and detailed source code.
5509Ausb
- 5509A USB通信代码架构，包含了枚举过程和初始化配置-RTL of 5509A USB,include emenue and initial
vertosysc
- verilog转换为systemc代码,用于RTL到系统建模-verilog to systemc
mpci32-verilog
- 一个32BIT 33/66MHz PCI CORE，verilog 的RTL CODEs-pci ipcore writen by verilog
PTO
- 飞思卡尔测速程序,PT0脉冲累计,RTL实DG128-DG128 PT0 interrupt cesu
rtc1302lcd
- 在tft彩屏上显示的基于ds1302 RTL的电子钟，2.4寸彩屏显示-In the TFT colour screens displayed on the ds1302 RTL based on the electric clock, 2.4 inch color display
mul1617
- 采用verilog RTL级语言，实现了有符号的16位乘17位的乘法器。特点是：采用流水的结构，可以在一个周期内处理完数据。通过QuartusII和Modulesim的功能仿真和时序仿真，并得到正确结果。-Realize the signs of 16 of the 17 patients take on time-multiplier. Features are: the structure of water, can be in a cycle processes the data. Thr