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rtl8019information
- rtl 8019 good information for beginners
rtl
- 这是FFT2048的源代码，是用verliog编写的-This is a FFT2048 the source code is written in verliog
mode
- modulus rtl code and synthesis example files
vhdl-tut
- Writing VHDL for RTL Synthesis
openvga
- 开源vga代码，包括rtl，验证工程等。-Vga source code, including rtl, authentication works.
oc8051_orig
- 8051 micro=contoller RTL
jpeg_decoder
- JPEG hardware decode RTL code
rtl-lxload-0.4
- Second-stage ELF boot loader for the Realtek RTL8181 SoC
Principles_of_Verifiable_RTL_Design
- 本书详细讲解了可验证的RTL级代码的原理，为编写RTL仿真测试程序提供了理论基础-This book gave a detailed RTL-level code verifiable principles for the preparation of RTL simulation test program provides a theoretical basis for
r8169
- 网卡8169驱动程序，基于ARM9平台的驱动-a realtek RTL-8169 gigabit ethernet diriver
DECOORG
- vhdl codings of decoder. data flow modelling, structural and behavioral modelling codes with their output waveform and rtl schematic.
pci_32tlite_oc
- 嵌入式 pci总线IP core的rtl源代码，用Verilog实现-Embedded pci bus IP core of the rtl source code, Verilog realization of
IU3
- sun公司的sparc结构之整数处理器vhdl源码-The file is the RTL of the Sparc s integer unit.
rtl
- this the generation of 48 pulses implementation in hdl language-this is the generation of 48 pulses implementation in hdl language
IIR
- 实验说明： 本次实验实现一个IIR滤波器，并在ISE里面仿真。 project目录里面是工程-Experiment descr iption: this experiment to achieve an IIR filter, and the ISE inside the simulation. \ rtl directory which is the source file \ project directory which is the project
seg
- 程序说明: 本次实验控制开发板上面的数码管。 \1-f文件夹里面的程序控制数码管从1开始显示，逐渐加1，一直到f。 \1234文件夹里面的程序控制数码管显示1234。 目录说明: 工程在\project文件夹里面 源文件和管脚分配在\rtl文件夹里面 下载文件在\download文件夹里面,.mcs为PROM模式下载文件,.bit为JTAG调试下载文件。-Procedure Descr iption: This development board above th
uart
- 程序说明: 本次实验控制开发板上面的串口，与PC机进行通信，并在串口精灵里面显示字符。 目录说明: 工程在\project文件夹里面 源文件和管脚分配在\rtl文件夹里面 下载文件在\download文件夹里面,.mcs为PROM模式下载文件,.bit为JTAG调试下载文件。-Procedure Note: The experimental control development board above the serial port to communicate wit
usb
- 程序说明: 本次实验控制开发板USB，与PC机进行通信，并在显示字符。 目录说明: 工程在\project文件夹里面 源文件和管脚分配在\rtl文件夹里面 下载文件在\download文件夹里面,.mcs为PROM模式下载文件,.bit为JTAG调试下载文件。-Procedure Note: In this experiment, control development board USB, and PC, to communicate, and display char
rtl
- 基于脉动结构的有限域乘法器，verilog代码-Based on the pulse of the structure of finite field multipliers, verilog code
GenDEC.RTL
- Tristate Bus -Tristate Bus Tristate Bus