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USB2.0_rtl_ipcore_verilog
- 经过门级网单验证的USB2.0 IP核 RTL代码-net after gate-level verification of USB IP Core RTL code
pcirtl
- 用verilog编写的pci——rtl级。-using Verilog prepared by the pci -- rtl level.
linux-2.4.20-rtl
- 该文件是rt_linux，实现linux的实时功能-rt_linux the document is to achieve real-time functional linux
equlizer
- 数字均衡器是通讯信道抗码间干扰的重要环节,这是一个用vhdl写的代码以及用SYNPLIFY8.0综合的RTL电路图 它包含三个模块FILTER,ERR_DECISION,ADJUST 希望对大家有用.-equalizer communications channel anti-inter-symbol interference an important link This is a use of the VHDL code to write and use SYNPLIFY8.0 integra
TabStrip_src
- A TabControl in the Visual Studio 2005 style, which supports correct Right-To-Left (RTL) and Left-To-Right (LTR) drawing-A TabControl in the Visual Studio 2005 STYL e, which supports correct Right-To-Left (RTL) an d Left-to-Right (LTR) drawing
RunTimePropertyViewer_src
- A TabControl in the Visual Studio 2005 style, which supports correct Right-To-Left (RTL) and Left-To-Right (LTR) drawing-A TabControl in the Visual Studio 2005 STYL e, which supports correct Right-To-Left (RTL) an d Left-to-Right (LTR) drawing
44b0_RT12864M
- ucos在三星s3c44b0上的rtl网卡程序-OUT Samsung s3c44b0 in the rtl card procedures
rtlinux-3[1].2-pre2
- fsmlabs的real time linux的内核，版本rtl-3.2-pre-fsmlabs the real time Linux kernel. rtl version - 3.2 - pre
spi_slic_driver
- linux下的SPI总线驱动程序，CPU是RTL的86系列，以legerity的SLIC chip为驱动对象。供大家参考。-linux under the SPI bus driver, the CPU is the RTL 86 series, legerity to the SLIC chip-driven targets. For your reference.
rs_decoder_31_19_6.tar
- Hard-decision decoding scheme Codeword length (n) : 31 symbols. Message length (k) : 19 symbols. Error correction capability (t) : 6 symbols One symbol represents 5 bit. Uses GF(2^5) with primitive polynomial p(x) = X^5 X^2 + 1
r1000_v1.05
- RTL 8168/8111 Driver for Linux
rtl
- last time when i came here to find some clock references. but most of them can not works well. so this files works well on FPGA board.-last time when i came here to find some clock references. but most of them can not works well. so this works well o
rgb2yuv
- verilog编写，rtl风格，流水线设计，实现图像rgb格式到yuv格式的转换。
rtl
- JTAG design verilog code.
ProtelSDK
- Protel99se SDK Protel向用户提供SDK软件包。SDK软件包包括：服务器生成向导和Protel API及相关文档资料。 服务器生成向导是一个运行于设计资源管理器的插入式服务器，它为用户生成第三方EDA软件模板的原代码和安装文件（.INS文件），安装文件用于将用户开发的第三方EDA软件安装在设计资源管理器平台上。服务器生成向导可以为用户生成两种格式的原代码：Delphi和C++ Builder。 为方便用户开发第三方EDA软件，Protel向用户提
RtlVclOptimize
- Delphi RTL-VCL optimization addon. I ve used, really good job.
Mc68000
- Mc68000 rtl code Simulation and Synthesis
mstr_mem32
- Master MemoryExamples for MT32 v1.0.0 Rtl core
pci_express_crc
- PCI express CRC rtl core for Fpga/asic Designer
64kMENU
- 8139 rtl 源代码--Source code for 8139 rt1.