搜索资源列表
2Dfft
- VHDL 关于2DFFT设计程序 u scinode1 ∼ scinode9.vhd: Every SCI node RTL vhdl code. The details can be seen in the following section. u 2dfft.vhd: The top module includes these scinodes and form a 3x3 SCI Torus network, and it support these sub-mo
IEEE-Std-1076.6-1999-VHDL-RTL-Synthesis
- IEEE Std 1076.6-1999 VHDL RTL Synthesis
Principles-of-Verifiable-RTL-Design
- 本书主要以HDL（verilog/vhdl）为例，详细讲述了在IC DESIGN FLOW中 Verification 以及Test的设计思想、方法和技巧，涵概了测试的各个方面， 是目前进行IC设计的同仁们最为推荐的一本宝典-(Kluwer) Principles of Verifiable RTL Design (2nd Ed.)
RTL
- 主要讲述的是发射机和接收机在RTL 仿真的时候，剔除DAC 和ADC 模块 进行无缝连接的模块说明-Focuses on the transmitter and receiver in RTL simulation time, excluding the DAC and ADC module Seamless connection module descr iption
uart transmission rtl level
- UART transmission rtl level
RTL
- UART RTL测试程序，用于串口调试，红色飓风E16开发板使用-UART RTL test procedures for serial debugging
RTL-coding-guidelines
- RTL coding guidelines Offer a collection of coding rules and guidelines. Make HDL Codes readable, modifiable, and reusable. Achieve optimal results in synthesis and simulation.
RTL
- HMI产品上使用的将黑白屏提升分辨率变为彩色屏的verilog RTL code-verilog RTL code for convert Black/White HMI to high resolution color
RTL
- UART 具有rtl ,实验测试可用，已用于实际工程中-UART has rtl, experimental tests are available, it has been used in the actual project
rtl
- Register Transfer Language (RTL) definitions for GCC.Value used by some passes to recognize noop moves as valid. -Register Transfer Language (RTL) definitions for GCC.Value used by some passes to recognize noop moves as valid.
RTL-ARM_-_RTX_Kernel
- RTL-ARM_-_RTX_Kernel实时操作系统内核的使用，可以作为RTX_Kernel的学习资料。-RTL-ARM _-_ RTX_Kernel use of real-time operating system kernel, as RTX_Kernel learning materials.
rtl
- SPI verilog RTL code
rtl
- RTL special definitions for ring0 & ring3 in one header.
rtl
- RTL special definitions for ring0 & ring3 in one header.
BCH-rtl-sourcecode
- BCH RTL 源代码，内容包括解码和编码，适合应用在需要纠错的芯片产品，已经在实际的芯片验证-BCH RTL Source Code, include encode and decode, verified in actual silicon
i2c_master
- verilog i2c master rtl+testbench 转自特权同学(verilog i2c master rtl+testbench)
i2c_slave
- Verilog i2c slave rtl + testbench 仿真ok(Verilog i2c slave rtl + testbench)
bnr
- 商业化高端视频画质芯片中的deblocking部分的RTL实现结构，实际工程的图。算法方面基本都是一样的。 同时可以把dnr一起在这里边同时做(deblocking rtl architecture for video processing)
rtlsdr_fm_discrim_demod_matlab
- Matlab 软件无线电 RTL-SDR FM解调。。。。。。。。。。。。(This scr ipt can be used to non-coherently demodulate an FM signal. The DSP operations carried out here are identical to those in the "rtlsdr_rx_fm_mono_bbox.slx" Simulink model)
Verilog数字系统设计
- verilog 数字系统设计 -RTL综合 测试平台与验证 的 随书光盘源程序(This rigorous text shows electronics designers and students how to deploy Verilog in sophisticated digital systems design)