搜索资源列表
bluetooth.tar
- 蓝牙的一个ip RTL 核,不知道对大家有没有用?谢谢。-this is an IP core of blutooth.
dspcbcjss1225
- C6000系列DSP体系结构介绍,介绍dsp的资料,对学习dsp非常有用-C6000 series DSP architecture, the introduction of information dsp, dsp very useful for studying
WATERHOURMETERBASEDONVHDL
- 在 MAX+PLUS II开发环境下采用 VHDL语言 设计并实现了电表抄表器 讨论了系统的四个 组成模块的设计和 VHDL 的实现 每个模块采用 RTL 级描述 整体的生成采用图形输入法 通过波形仿真 下载芯片测试 完成了抄表器的功能-In the MAX+ PLUS II development environment using VHDL language design and implementation of the meter meter reading device to di
Semaphore
- Show hou use semaphores in RTL-ARM
counter
- 详细描述n比特计数器及RTL验证,计数器的位宽用generic语句设置为参数。MY_CNTR是一个n比特二进制的计数器,可以向上向下计数,并可设置计数值,计数器用异步的方式进行低电平复-A detailed descr iption of n-bit counter and RTL verification, the bit counter is set to use generic parameters statement. MY_CNTR is an n-bit binary counter
78F0413demo
- nec 78F0413的例子程序,里面有LCD,RTL和PORT的操作,学NEC的朋友可以使用-nec 78F0413 demo,it has the lcd,rtl and port driver, it will help you who need to learn the nec
mcu_8
- 使用函数实现简单的八位处理器 软件开发环境:ISE 7.1i 仿真环境:ISE Simulator 1. 这个实例实现通过ISE Simulator工具实现一个可以进行两个八位操作数四种操作的简单处理器; 2. 工程在project文件夹中,双击mpc.ise文件打开工程; 3. 源文件在rtl文件夹中,mpc.v为设计文件,mpc_tb.tbw是仿真波形文件; 4. 打开工程后,在工程浏览器中选择mpc_tb.tbw,在Process View中双击“Si
sparc
- sparc org, vhdl rtl code
5
- 介绍了一种嵌入式以太网接口的设计方案, 采用微控制器SPCE500 A 与以太网控 制芯片RTL 8019A S 进行硬件电路连接, L’nSPTM IDE 上采用嵌入式汇编进行软件设计, 并给 出了有关的硬件框图及程序片断.-Introduced an embedded Ethernet interface design, SPCE500 A micro-controller with the Ethernet controller chip RTL 8019A S connected
A_bit_serial_data_transmitter
- 比特序列传送模块 把输入的八位比特数据 做循环后每个比特输出 详细请看英文描述-• To create Verilog-HDL modules written in the RTL style appropriate for both simulation and synthesis, for the various component parts of an Asynchronous Serial Data Transmitter. • To verify th
TRL_Design_of_a_asynchronous_bit_serial_data_trans
- RTL 异步数据传送模块 用verilog HDL 语言描述 输入为八比特数据,执行操作后异步每比特输出。-• To create Verilog-HDL module written in the RTL style appropriate for both simulation and synthesis, for an Asynchronous Serial Data Transmitter. • To verify the correct behavi
efcount
- 完整的等精度频率相位计,包含了项目文件、VHDL源代码、RTL电路图-Such as the complete phase of the frequency accuracy, including the project document, VHDL source code, RTL circuit
easily_frequency_dividing
- 教你用各种方法实现分频,实现良好的时序。个你的RTL开发增加经验-teach you how to frequency divide
extension_pack_latest.tar
- This project contains files you can use to expand upon the basic IEEE packages you normally use for creating testbenches and RTL code.
Verilog
- verilog HDL语言使用手册,包括:语法规则,RTL设计思想和方案等-verilog HDL language user manual, including: grammar rules, RTL design ideas and programs
multi
- VHDL Multiplier RTL code-VHDL Multiplier RTL code
USB2.0
- USB2.0行为级描述,挂接在AMBA AXI总线上-USB2.0 RTL discr iption
rtl
- 按WTL方式封装miniGUI的窗口界面库,在uClinux+miniGUI1.3.3上调试通过,并运行良好.-WTL package by way of a window interface library miniGUI in uClinux+ miniGUI1.3.3 through debugging, and running good.