搜索资源列表
sdram
- 程序说明: 本次实验控制开发板上面的SDRAM完成读写功能。 先向SDRAM里面写数据，然后再将数据读出来做比较，如果不匹配就通过LED变亮显示出来，如果一致，LED就不亮。 part1是使用Modelsim仿真的工程 part2是在开发斑上面验证的工程 目录说明: part1: part1_32是4m32SDRAM的仿真工程 part1_16是4m16SDRAM的仿真工程 \model文件夹里面是仿真模型 \rtl文件夹里面是源文件 \sim文
EMCRTL
- RTL Code for Design of Extarnal Memory Controller for Accessing Asynchronous SRAM of size 512Kx16
LIP1611CORE_AES128_SEC_UWB
- AES 128 Synthesisable RTL code
LIP6495CORE_mpeg_sub_picture
- MPEG sub picture RTL code
LIP6488CORE_vdec_h264_intra
- H264 Compress Intra RTL code
rtl
- RTL special definitions for ring0 & ring3 in one header.
Filtra3
- Noise Canceller since C to VHDL RTL authomatic generation throught CoDeveloper by Impulse
RTL8305SB-DEMOBOARD-SCH128P2L-V-2009
- RTL 8305sb demo schematic board fot 5 port switch
RTL-to-Gates-Synthesis-using-Synopsys-Design-Comp
- RTL-to-Gates Synthesis using Synopsys Design Compiler.rar
I2C_Verilog_Model
- 该源程序包是I2C的Verilog语言模型，包括以下4个部分：RTL源代码，测试平台，软件仿真代码，说明文件。-This source package is I2C bus model based on Verilog language. It has the following 4 parts: RTL code, testbench, sofeware simulating code, help document.
SD_Controller_Verilog
- 该程序包是SD卡/MMC卡控制器SDC的verilog语言包，它包括以下4部分：RTL源代码，测试平台，软件仿真文件，说明文件。-This source package is the SD card and MMC card controler model based on the Verilog language. It has the following 4 parts: RTL language, testbench, software simulating files and help
Verilog-Digital-System-Design
- Verilog数字系统设计——RTL综合.测试平台与验证 书中的所有源代码-Verilog Digital System Design- RTL synthesis. Test and verification platform for all the source code for the book
spi_driver_verilog
- SPI控制器RTL级源码，实现标准SPI硬件接口-SPI controller RTL-level source code to achieve the standard SPI hardware interface
interpolation-filer-rtl
- synthesizable verilog rtl implemetation of interpolation filter, for both asic and fpga. 64x interpolation. interp_filter.v interp_first.v interp_second.v interp_third.v upsample.v
Principles-of-Verifiable-RTL-Design
- RTL可验证性设计的经典书籍，由惠普大牛撰写！-RTL the verifiability design classic books written by the Hewlett-Packard, Daniel!
Verilog-digital-system-design-RTL-synthesis-testb
- verilog book. RTL sysnthesis testbech
verification-of-SLM-and-RTL
- VERIFICATION OF SLM AND RTL
rtl.tar
- This RTL of Router by uisng verilog-This is RTL of Router by uisng verilog
rtl
- This is also RTL of router by using another type of method
IEEE-Std-1364.1-2002-Verilog-RTL-Synthesys
- IEEE Std 1364.1-2002 Verilog RTL Synthesys