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FAQ
- RTL8019设计时将会遇到的问题及其解答，相信会对你有所帮助-8019 RTL
wishbone_m4_s8
- wishbone 骨幹部份 RTL 源碼, 以verilog 寫成, 自創. 支源 4 master 及 8 slave-wishbone core, write by verilog, support 4 master and 8 slaver. language: verilog.
FIR
- The first three examples illustrate the difference between RTL FSMD model (Finite State Machine with Datapath buildin) and RTL FSM + DataPath model. From view of RT level design, each digital design consists of a Control Unit (FSM) and a Datapath. Th
LIP6492CORE_zigzag
- Compression ZingZang RTL Verilog source code
mem-ctrl-rtl
- 实现对ddr的控制，可以在fpga的仿真环境下跑程序，并有testbench可以参考-implement ddr control
mem-if-rtl
- 实现memory的interface，就是memory的接口实现，可以在fpga上进行综合仿真-Achieve the memory of the interface, is the memory of the interface, you can fpga on the integrated simulation
xge_mac
- 10G MAC ip核源码其中包含了三个版本。经过测试正确无误。-======================== 10GE MAC Core ======================== ------------------------ 1. Directory Structure ------------------------ The directory structure for this project is shown below.
DSPBuilderusemathord
- DSP Builder是一个系统级（或算法级）设计工具，它架构在多个软件工具之上，并把系统级（或算法仿真建模）和RTL级（硬件实现）两个设计领域的设计工具连接起来，都放在了Matlab/Simulink图形设计平台上，而将QuartusII作为底层设计工具置于后台，最大程度地发挥了这种工具的优势。-DSP Builder is a system-level (or algorithm-level) design tool architecture in a number of software
mc8051_top
- 利用synplify8.1综合的8051IPcore电路图，可用synplify打开查看电路-8051 RTL Schematic
cwdl374s
- cc386编译器源代码的最新版本，其他参照其英文说明-This package is the sources for my DOS C compiler and related tools. See license.txt and copying for licensing information See relnotes.doc for release notes use pkunzip-d to install these files These co
CoreCORDIC_DS
- cordic rtl generator for generating different cordic arithmetic
FullAdder
- 要求在Quartus II软件，利用VHDL完成层次式电路设计，电路中的元件可以用VHDL设计也可以用库元件连线构成再封装。借助EDA工具中的综合器，适配器，时序仿真器和编程器等工具进行相应处理。输入方法不限制。适配采用Cyclone系列的EP1C6Q240C8。要求综合出RTL电路，并进行仿真输入波形设计并分析电路输出波形。要求采用层次式结构设计。-Quartus II software requires the use of VHDL complete hierarchical circui
avalon_rtl8019
- rtl8019 lwip 驱动，nios ii处理器 uC/os -rtl8019 lwip 驱动，nios ii处理器 uC/os II
ac97_latest.tar
- ac97的verilog实现，包含详细的代码实现以及仿真，非常可靠-ac97，verilog rtl
usb1.tar
- usb1.1 完整代码, 包含 PHY 等所有的 代码 已经在 VCS, NCSIM 的环境下仿真过了，-usb1.1 full rtl and test
64R4SDFpoint_FFT
- 该工程实现了一个64点FFT，verilog编写，采用R4SDF结构，通过Modelsim功能仿真，压缩包里有rtl代码，dc脚本，输出报告。-The project implements a 64-point FFT, verilog compiled by R4SDF structure, through the Modelsim functional simulation, compression bag with rtl code, dc scr ipt, the output repo
64pointFFTR2MDC
- 该工程实现了一个64点DIF FFT，verilog编写，采用R2MDC结构，通过Modelsim功能仿真，压缩包里有rtl代码，dc脚本，输出报告。-The project implements a 64-point DIF FFT, verilog compiled by R2MDC structure, through the Modelsim functional simulation, compression bag with rtl code, dc scr ipt, the out
opencore_fft.tar
- the fft project from opencore. they are rtl code.
rtl
- 基于VERILOG的SDRAM控制程序，是目前主流设计方法-Control procedures based on VERILOG of SDRAM, is the main design