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FullAdder
- 要求在Quartus II软件，利用VHDL完成层次式电路设计，电路中的元件可以用VHDL设计也可以用库元件连线构成再封装。借助EDA工具中的综合器，适配器，时序仿真器和编程器等工具进行相应处理。输入方法不限制。适配采用Cyclone系列的EP1C6Q240C8。要求综合出RTL电路，并进行仿真输入波形设计并分析电路输出波形。要求采用层次式结构设计。-Quartus II software requires the use of VHDL complete hierarchical circui
avalon_rtl8019
- rtl8019 lwip 驱动，nios ii处理器 uC/os -rtl8019 lwip 驱动，nios ii处理器 uC/os II
ac97_latest.tar
- ac97的verilog实现，包含详细的代码实现以及仿真，非常可靠-ac97，verilog rtl
usb1.tar
- usb1.1 完整代码, 包含 PHY 等所有的 代码 已经在 VCS, NCSIM 的环境下仿真过了，-usb1.1 full rtl and test
64R4SDFpoint_FFT
- 该工程实现了一个64点FFT，verilog编写，采用R4SDF结构，通过Modelsim功能仿真，压缩包里有rtl代码，dc脚本，输出报告。-The project implements a 64-point FFT, verilog compiled by R4SDF structure, through the Modelsim functional simulation, compression bag with rtl code, dc scr ipt, the output repo
64pointFFTR2MDC
- 该工程实现了一个64点DIF FFT，verilog编写，采用R2MDC结构，通过Modelsim功能仿真，压缩包里有rtl代码，dc脚本，输出报告。-The project implements a 64-point DIF FFT, verilog compiled by R2MDC structure, through the Modelsim functional simulation, compression bag with rtl code, dc scr ipt, the out
opencore_fft.tar
- the fft project from opencore. they are rtl code.
rtl
- 基于VERILOG的SDRAM控制程序，是目前主流设计方法-Control procedures based on VERILOG of SDRAM, is the main design
rtl8185_linux_26.2007
- RTL 8185 Liunx驱动程序 适用于不能识别网卡时安装-RTL 8185 Liunx drive
rtl
- 这是一个在FPGA开发板上已经测试通过的程序，是关于跑马灯的程序，对初学者很有用。-This is an FPGA development board has been tested through the process, is on the marquees of the program, useful for beginners.
ASIC
- 本文介绍了基于标准单元库的深亚微米数字集成电路的自动化设计流程。此流程从 设计的系统行为级描述或 RTL 级描述开始，依次通过系统行为级的功能验证，设计综合，综合后仿真，自动化布局布线，到最后的版图后仿真。在-This article describes the standard cell library based on deep sub-micron digital IC design flow automation. This process from the design of sy
RTL8019ASDemo2
- 单片机控制RTL8019AS实现以太网接口实例，改程序用C编写。原理图用protel设计。 包括以太网初始化程序、发送程序和接收数据程序。 单片机系统为整个电路的主处理部分，其作用主要包括对以太网接口芯片的初始化配置 以及以太网数据的发送和接收控制。-SCM RTL8019AS Ethernet interface, an instance, change program written with C. With protel schematic design
FPGA
- FPGA入门教程包含数字电路基础FPGA简介FPGA开发流程RTL设计QuartusII设计实例和仿真-FPGA Tutorial Introduction contains digital circuits based on FPGA FPGA RTL design development process, design example and simulation QuartusII
Synopsys-RTLSystemC
- synopsys的systemc和RTl书籍清晰电子版，专业权威的EDA公司的培训资料-synopsys of systemc and RTl clear electronic version of books, professional authority of the EDA company' s training materials
Example-b4-1
- Altera基本宏功能的产生和实现方法.定制一个双端口RAM，DualPortRAM,Quartus II仿真器中做门级仿真,在ModelSim中对这个工程进行RTL级仿真.-Altera basic macro functionality of the generation and realization. Customize a dual-port RAM, DualPortRAM, Quartus II simulator to do gate level simulation, on t
FarsiTextBox
- Textbox suitable for persian and arabian and all RTL languauge.
Traffic
- hotpower编写的lpc213x系列arm7芯片的头文件及简单RTL例程。-hotpower prepared lpc213x series arm7 chip RTL header files and simple routines.
FastCode
- *** *** *** *** *** *** **** *** **** FastCode Libraries ********** **************************************** .. What is does .. The following library will replace the current RTL code used by your application(s) with faster and
16bitmultiplier
- 集成电路测试向量生成代码。测试ISCA-85中的c6288电路,算法针对RTL电路测试来生成测试向量。-VISL Circuits test patterns gernarator
VHDLvsVerilog
- This document is in two parts. The first part takes an unbiased view of VHDL and Verilog by comparing their similarities and contrasting their differences. The second part contains a worked example of a model that computes the Greatest Common Divisor