搜索资源列表
FIFO_TEST
- XILINX FIFO IP核测试程序,已经通过测试,方便可用-XILINX FIFO IPcore testbench
CLA_20
- 用verilog语言编写的CLA_20文件。CLA_20是20位超前进位加法器的源代码,该代码验证后功能正确,读者可以自行编写testbench代码进行验证。-With verilog language CLA 20 files. CLA 20 is 20 lookahead adder source code after the code verification function correctly, readers can write their own testbench code fo
CLA_4
- 用verilog语言编写的CLA_4文件。CLA_4是4位超前进位加法器的源代码,该代码验证后功能正确,读者可以自行编写testbench代码进行验证。-With verilog language CLA 4 files. CLA 4 is a four-ahead adder source code after the code verification function correctly, readers can write their own testbench code for ver
qpsk
- QPSK调制程序的testbench程序 timescale 1ns/1ns //单位时间,时间精度 module qpsk_tb //qpsk调制的testbench reg clk reg rst reg x wire y -QPSK modulation program testbench program timescale 1ns/1ns // unit of time, time accuracy module qpsk_tb // qps
chuzuche
- 出租车vhdl程序,并带有testbench仿真程序,通过开始按键复位,然后根据行使信号进行公里计数,起步价3公里8元钱,超过3公里一公里1元钱-Taxi vhdl program, with a testbench simulation program, started by the reset button, then the exercise kilometer count signal, starting at 3 km 8 yuan, more than three kilometer
inout
- 用于RAM的测试文件,以及testbench-some RAM testingfiles,and its testbench
adder_carry_chain
- 使用verilog语言实现进位链加法器,quartus下编译,并使用modelsim进行了验证,内含carry_chain.v代码文件以及testbench文件-use verilog language,carry_chain adder
Vhdl_testbench
- vhdl 的testbench编写教程,英文ppt以及源码工程-Write tutorials, as well as English ppt Source of engineering vhdl testbench
DES-Verilog-master
- DES加密算法硬件verilog实现,包含testbench,加密主模块encrypt,明文变换模块LRToCiphertextConverter,NextRi模块等子模块。-DES encrypt verilog
apbtoaes128_latest.tar
- AES加密算法verilog代码实现,基于APB总线接口数字IP,包含详细的testbench-AES encryption algorithm verilog code, based on the APB bus interface digital IP, contains a detailed testbench
apbi2c_latest.tar
- APB总线协议转I2C总线协议的接口IP,verilog代码实现,包含详细testbench-APB bus interface to I2C bus interface IP,verilog code
UART-master
- UART通讯接口verilog代码实现,uart_tx子模块和uart_rx子模块,包含详细testbench-UART interface verilog code, uart_tx、uart_rx, testbench
gpio-master
- 基于WISHBONE总线接口的GPIO模块verilog代码实现,包含详细GPIO定义文档,testbench,RTL仿真与综合环境-WISHBONE interface to GPIO verilog code, GPIO define, RTL sim, syn
testbench.sv
- RS 编码和解码Verilog Code, 实现了RS(544,514)的编码和译码;--RS Coding and Decoding Verilog code, implement RS(544,514)
ddr_controller
- 完整的DDR控制器设计,包含代码、仿真环境、FPGA综合网表等-full DDR controller ip,include rtl code,simulation environment and testbench, fpga synthesis netlist,etc.
memTB
- it is a testbench describing the function of a memory
VHDL_4bit_magnde_compar_code_testbench
- this a vhdl testbench for a 4 bit magnitude comparator that comprises all the stimuli a 4 bit magnitude comparator function table.-this is a vhdl testbench for a 4 bit magnitude comparator that comprises all the stimuli a 4 bit magnitude comparator
double_addsub
- 双字的加减法的verilog源代码和testbench,已经过测试-verilog source code and testbench double word addition and subtraction, and has been tested
pipeline_add
- pipeline式累加器的verilog代码和testbench文件,已验证-pipeline type accumulator verilog testbench code and documents, verified
gray_counter
- altera官方格雷码计数器的verilog代码和testbench,已测试-altera official Gray code counter verilog code and testbench, have been tested