搜索资源列表
textio
- vhdl testbench的编写，textio的编写是一个难点，也是一个重点，而这是本人搜集的多篇关于textio的文章，同时附有简单注释!
flash接口控制_verilog
- flash接口控制器的VHDL以及verilog源代码和Testbench程序-flash interface controller VHDL and Verilog source code and procedures Testbench
vhdl实现alu的源代码
- VHDL实现ALU的源代码，并且提供了一个详细的testbench！-ALU VHDL source code, and provide a detailed testbench!
pll
- 用VHDL写的数字锁相环程序 pll.vhd为源文件 pllTB.vhd为testbench-pll.vhd : PLL written in VHDL hardware language. pllTB.vhd is a test program for pll.vhd.
VHDL_Testbench
- VHDL中TestBench的编写，很详细，有例程
16QAM_verilog 使用Verilog实现全数字的16QAM调制器
- 使用Verilog实现全数字的16QAM调制器，假设载波的频率为1MHz，数据比特率为100kbit/s.包括源代码和testbench-use verilog to realize 16qam,carrier frequency is 1MHz,data rate is 100kbit/s.including source code and testbench
sha-1.rar
- 本算法基于leon2协处理器接口标准，内含testbench，在modelsim中仿真通过，在ise9.2中综合及后仿真通过。,The algorithm is based on the leon2 co-processor interface standard, including testbench, ModelSim simulation in the adoption, in ise9.2 integrated and adopted after the simulation.
hssdrc_latest.tar.gz
- HSSDRC IP core is the configurable universal SDRAM controller with adaptive bank control and adaptive command pipeline. HSSDRC IP core and IP core testbench has been written on SystemVerilog and has been tested in Modelsim. HSSDRC IP core is li
rs_decoder_31_19_6_latest.tar.
- RS解码器的FPGA实现，有TestBench,RS decoder FPGA to achieve, there TestBench
FPGA-PCI.rar
- 基于FPGA的PCI接口源代码及Testbench Verilog程序代码,fpag pci
SRAM.rar
- 瑞芯科技EFX400SL开发板上使用SRAM的工程源码,Rockchip EFX400SL the development of science and technology the use of SRAM on-board source of project
pn_generator.rar
- FPGA实现pn发生器，Verilog代码实现，另带modlesim的仿真测试文件，很有价值。,FPGA realization of pn generator, Verilog code, and the other with the simulation test modlesim documents of great value.
sram
- sram操作vhdl源程序，内有sdram模型，控制器设计，及测试源程序-sram operating in vhdl \doc DDR SDRAM reference design documentation \model Contains the vhdl SDRAM model \route Contains the Quartus 2000.05 project files a routed controller design \simulation
Chapter10
- 第十章的代码。 本书通过100多个模块实例，详细地讲解了Verilog HDL程序设计语言，全书共分13章，内容涉及VerilogHDL语言基本概念、建模、同步设计、异步设计、功能验证等，实例包括各种加法器/计数器、乘法器/除法器、编码器/译码器、状态机、SPIMaster Controller、I2C Master controller、CAN ProtocolController、Memory模块、JPEG图像压缩模块、加密模块、ATA控制器、8位RISC-CPU等及各个实例模块相
adder
- 一个最简单的加法器，带testbench-One of the most simple adder with testbench
verilog--maopao-paixu
- 用verilog实现的冒泡排序法 ，有testbench-Implemented using verilog bubble sort, there is testbench
VHDL_Testbench
- Altera官方的VHDL_Testbench教程,想学怎么写Testbench的话,强烈建议看一看。（英文的文档，不过都不难。耐心看完吧！）-Altera official VHDL_Testbench tutorial, want to learn how to write Testbench, then strongly recommended that a look. (English document, but are not difficult. The patience to re
mp3decoder
- verilog实现mp3解码程序，包括testbench-mp3 decoder verilog implementation procedures, including the testbench
verilog_sdram_controller_testbench
- SDRAM 控制器 ，Verilog版本的，带有完整的SDRAM 仿真模型，testbench等，能够实际使用，并且利于学习-The SDRAM controller is designed for the Virtex V300bg432-6. It s simulated with Micron SDRAM models. The design is verified with backannotated simulation at 125MHz