搜索资源列表
LED.VHDL
- LED控制VHDL程序与仿真 分别介绍采用FPGA对LED进行静态和动态显示的数字时钟控制程序-LED control procedures and VHDL simulation briefed on the use of FPGA LED static and dynamic significantly the figures show clock control procedures
TLC5510.VHDL
- TLC5510 VHDL控制程序 基于VHDL语言,实现对高速A/D器件TLC5510控制-TLC5510 VHDL control procedures based on the VHDL language, to achieve high-speed A / D control device TLC5510
ASK.VHDL
- ASK调制VHDL程序及仿真 基于VHDL硬件描述语言,对基带信号进行ASK振幅调制-ASK modulation VHDL simulation based on the procedures and VHDL hardware descr iption language, the baseband signal amplitude modulation ASK
MASK.VHDL
- MASK调制VHDL程序与仿真 基于VHDL硬件描述语言,对基带信号进行MASK调制-MASK modulation VHDL simulation based on the procedures and VHDL hardware descr iption language, the baseband signal modulation MASK
PSK.VHDL
- CPSK调制VHDL程序及仿真 基于VHDL硬件描述语言,对基带信号进行调制-CPSK modulation VHDL simulation based on the procedures and VHDL hardware descr iption language, the baseband signal modulation
i2c_code(vhdl)
- i2c源码vhdl语言编写,传上与大家分享,请多指教-i2c source VHDL language, communicating with everyone sharing, please enlighten
vhdl-2
- UART 的VHDL源代码。可在ISE, Max-Plus II,等开发环境下实现。-UART VHDL source code. The ISE, Max-Plus II, and other development environments under.
VHDL-Clock
- 用VHDL语言写的时钟程序。采用模块化编程。可在EPM7128芯片上下载。编译环境可用Maxplus或Quartus。-write VHDL clock procedures. Modular programming. The EPM7128 chips download. Build environment or Quartus Maxplus available.
可综合的vhdl设计特点
- 可综合的vhdl设计特点.pdf-synthesizable VHDL design features. Pdf
1024点FFT快速傅立叶变换(vhdl)
- 1024点FFT快速傅立叶变换,(vhdl代码)-1024-point FFT vhdl
VHDL的基本数学运算库
- VHDL的基本数学运算库,非常好用-VHDL basic arithmetic library, a very handy! !
一篇用VHDL实现快速傅立叶变换的论文
- 一篇用VHDL实现快速傅立叶变换的论文,包括原理分析和代码实现,印度圣雄甘地大学M.A.学院提供-VHDL with a Fast Fourier Transform papers, including the principle of analysis and implementation of the code, the Mahatma Gandhi Institute of the University of Marat
VHDL实例
- 各种常用模块的VHDL描叙实例,PDF格式-various modules used VHDL depicts examples, PDF format
some-usful-vhdl-source-code
- 一些实用的VHDL源码,有各种信号调制的,还有LCD控制的,出租车计价器等等源码。-some practical VHDL source code, a variety of signal modulation, there is the LCD control. taximeters, etc. source.
chengxu(vhdl)
- 这是用VHDL编写的FPGA与计算机进行串口通信的程序和一个LED程序-VHDL and FPGA prepared by the computer serial communication procedures and an LED procedures
fenpin(vhdl)
- 使用VHDL编写的分频程序,能进行任意次的偶数分频,程序简单易懂,供 初学者参考-prepared by the use of VHDL-frequency procedures can make even the random frequency, the procedures are simple and easy to understand. reference for beginners
decoder(vhdl)
- 这是用VHDL编写的译码程序,程序简单易懂-VHDL prepared decoding procedures that are simple to understand
VHDL-FPGA-clock
- FPGA数字钟的设计,用VHDL语言编程,max+plus仿真,可在实际电路中验证-FPGA design, VHDL programming, max plus simulation, in the actual circuit verification
ref-ddr-sdram-vhdl
- 本程序是DDR SDRAM控制器的VHDL程序,由ALTERA 提供-this procedure is DDR SDRAM controller VHDL procedures provided by Altera
VHDL-ysw
- 基于CPLD的棋类比赛计时时钟,第一个CNT60实现秒钟计时功能,第二个CNT60实现分钟的计时功能,CTT3完成两小时的计时功能。秒钟计时模块的进位端和开关K1相与提供分钟的计时模块使能,当秒种计时模块计时到59时向分种计时模块进位,同时自己清零。同理分种计时模块到59时向CTT3小时计时模块进位,到1小时59分59秒时,全部清零。同时,开关K1可以在两小时内暂停秒钟计时模块,分钟计时模块和小时计时模块。各模块的VHDL语言描述如下:-CPLD-based time clock chess c