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VHDL语言100例详解
- VHDL语言100例详解。详细讲解了用VHDL语言进行数字电路和数字系统设计的知识。用100个实例，不仅进行基础的门电路设计，而且还有较为复杂的数字系统设计。这些实例可以直接被调用。-VHDL Elaborates on 100 cases. Detailed account of VHDL for digital circuits and digital systems design knowledge. With 100 examples, not only for infrastructu
FPGA_SONGER
- 基于FPGA的乐曲硬件演奏电路设计的实现，有完整的VHDL代码，并有PDF详细说明如何下载及跳线设置，并“梁祝”在GW48系列开发平台上下载调试成功。音乐优美-FPGA-based hardware music concert circuit design to achieve a complete VHDL code. and a detailed account of how the PDF download and set up the jumper, and "Butterfl
FPGA_TENNIS
- 基于FPGA的乒乓球游戏硬件电路的设计与实现，有完整的VHDL代码，并有PDF详细说明如何下载及跳线设置，并在GW48系列开发平台上下载调试成功-FPGA-based table tennis game hardware circuit design and realization of a complete VHDL code. and a detailed account of how the PDF download and jumper settings and in a series
Filter-Wiz-PRO-3.2aCrack
- 本人使用次数最多的分立元件滤波器软件,功能非常齐全,基本能想到的问题它都替你考虑到了,唯一缺点是不注册的话对极点数和阻值作了一定的限制-I have the highest number of discrete components using filter software is very complete, it can basically think of the problem are taken into account for you, the only drawback is no
dff
- 用vhdl编写的D触发器，锁存器等，不需帐号就可自由下载此源码-VHDL prepared using D flip-flops, latches and so on, no account can be a free download this source
Verilog_HDL
- Verilog HDL程序设计教程,以可综合的设计为重点，同时对仿真和模拟也作了深入阐述。全面介绍了verilog HdL 词法，语法。-Verilog HDL Programming Guide, to be designed as an integrated focus on simulation and simulation at the same time also made to describe further. Verilog HdL gave a comprehensive ac
EDA-basedtechnologiessuchasprecisionmulti-function
- 在对三种测频方法进行分析的基础上，介绍了基于EDA技术的等精度测频原理。给出采用AT89C51实现控制并通过FPGA来设计多功能等精度数字频率计的具体方法。该频率计可以兼顾频率计对速度、资源和测频精度等各方面的优化需求。-Frequency of three methods of analysis based on EDA technology based on the principle of frequency measurement accuracy, etc.. AT89C51 give
account
- Verilog 实现的电话计费器 信号定义：decide： 电话局反馈回来的信号，代表话务种类，“01”表示市话，“10”表示长话，“11”表示特话；-Verilog-based telephone billing device
pinlvji
- 考虑到只基于单片机的频率测量计设计主要是以单片机为基础，原理简单，但由于自身精度问题，测量的范围小。而基于FPGA和单片机结合的频率测量设计主要是以单片机作为系统的主控部件，FPGA完成对时序逻辑控制、计数功能，能较好的利用了FPGA的高精度、高速等方面的优势。-Taking into account only single-chip based on the frequency meter is based on single-chip design based on a simple pri
key
- Verilog HDL编写的键盘扫描程序，考虑了判断按键弹起的问题。程序按一定的频率用低电平循环扫描行线，同时检测列线的状态，一旦判断有一列为低则表示有键被按下，停止扫描并保持当前行线的状态，再读取列线的状态从而得到当前按键的键码；等待按键弹起：检测到各列线都变成高点平后，重新开始扫描过程，等待下一次按键。-Written in Verilog HDL keyboard scanner, taking into account to determine key bounce problem. P
account
- 手机话费记录，通过状态机实现不同通话类型的手机话费记录功能-Their phone records, through the state machine to achieve different types of their phone call logging
crossroute-R4
- As integrated circuits are migrated to more advanced technologies, it has become clear that crosstalk is an important physical phenomenon that must be taken into account. Crosstalk has primarily been a concern for ASICs, multi-chip modules, and
CounterUni
- Universal counter written on VHDL in Quartus II. It counts up and down by taking into account overflow and onderrun bits.
zhuantaiji
- 简单的状态机设计，功能是检测一个5位二进制序列“10010”。考虑到序列重叠的可能，有限状态机共提供8个状态（包括初始状态IDLE）。-Simple state machine design, function is to detect a 5-bit binary sequence " 10010." Taking into account the possibility of overlapping sequences, finite state machines prov
chuzuche
- 本程序使用verilog语言编写的出租车计价系统，实现时距并计！主要用状态机来实现！-This program uses the taxi meter verilog language system, and taking into account the time-distance! State machine is mainly used to achieve!
Example-4-8
- always模块的敏感表为电平敏感信号的组合逻辑电路 这种形式的组合逻辑电路应用非常广泛，如果不考虑代码的复杂性，几乎任何组合逻辑电路都可以用这种方式建模。always模块的敏感表为所有判定条件和输入信号，请读者在使用这种结构描述组合逻辑时，一定要将敏感表写完整。在always模块中可以使用if…else…、case、 for循环等各种RTL关键字结构 assign等语句描述的组合逻辑电路 这种形式的组合逻辑电路适用于描述那些相对简单的组合逻辑，信号一般被定义为wire型，常用
pinlvji
- AT89c51 1602 可以分频的频率计，最大可以测量98MHZ,程序部分设计得精良！-AT89 c 511602 the frequency that can divide repeatedly account, biggest can measure a 98 Mhz, the procedure part designs excellent!
account
- 电话计费器程序，显示卡内余额， 显示本次通话的时长；余额过少时的告警信号。当告警时间过长时自动切断通话信号。-Telephone billing program, showing the balance of the card, the time of the call balance too came from the alarm signal. Automatically when the alarm time is too long to cut off the call signal.
PipelineCPU
- 用Verilog HDL语言或VHDL语言来编写，实现多周期CPU设计。能够完成以下二十二条指令。（均不考虑虚拟地址和Cache，并且默认为大端方式）： add rd, rs, rt addu rd, rs, rt addi rt, rs, imm addiu rt, rs, imm sub rd, rs, rt subu rd, rs, rt nor rd, rs, rt xori rt, rs, imm clo clz slt rd, rs, rt
mulitcpu
- 用verilog HDL语言或者VHDL语言来编写，实现多时钟周期CPU的设计。能够完成以下二十二条指定（均不考虑虚拟地址和Cache，并且默认为小端方式）： add rd, rs, rt addu rd, rs, rt addi rt, rs, imm addiu rt, rs, imm sub rd, rs, rt subu rd, rs, rt nor rd, rs, rt xori rt, rs, imm clo clz slt rd, rs,