搜索资源列表
FIFO_v
- FIFO的verilog实现,内附testbench和文档说明-FIFO verilog achieve, enclosing testbench and documentation shows
FIFO_Syn
- 同步FIFO功能,verilog语言描述,通过了modelsim 6.0 仿真,Quartue综合
fifo
- 使用Verilog语言编写,把FPGA配置成一个fifo
afifo
- 异步fifo的verilog程序,含有测试平台
16550
- UART16550兼容的串行通讯控制器,Verilog语言描述,采用Altera Cyclone系列芯片实现FPGA综合,因为FIFO部分利用到内部资源实现。已经在某项目中成功应用,特此推出。
FIFO_Example2
- 用Verilog语言写的FPGA FIFO,仅供参考。
实用verilog代码(乘法器,触发器,FIFO等)
- 本文件包含一些实用verilog程序代码,包括乘法器,除法器,伽罗瓦域乘法器,CORDIC数字计算机的设计,异步FIFO设计,伪随机序列应用设计,RS(204,188)译码器的设计,都是可综合的。对研究这部分的朋友有一定的帮助。
Verilog_CY7C68013-SLAVE-FIFO
- 用VERILOG 编写 CY7C68013 usb数据采集SLAVE FIFO模式驱动程序 ,已验证过-Prepared with the VERILOG CY7C68013 usb data acquisition SLAVE FIFO mode driver, has proven
fifo_32_4321.rar
- 用verilog写的输出数据宽度可变的FIFO,输入数据为32-bit,输出数据可以配置为4-1任意bit。有设计文件和testbench,Use verilog to write a variable width of the output data FIFO, input data for the 32-bit, output data can be configured as 4-1 arbitrary bit. There are design files and testbench
FIFO64
- FIFO级联,利用verilog语言实现Xilinx FIFO18单元的多个级联,增大FIFO深度。-FIFO cascade, using Verilog Xilinx FIFO18 language to achieve a number of cascade units, increasing the FIFO depth.
FIFO_8_8
- FIFO先进先出队列,一种缓存、或一种管道、设备、接口(Verilog HDL程序,内附说明)-FIFO FIFO queue, a cache, or a pipeline, equipment, Interface (Verilog HDL program, containing a note)
asfifodesign
- 异步fifo设计文档,里面包括详细的verilog设计方案及代码。fifo设计是通信中必然设计的设计-a fifo design with code inside, using verilog language
fifo
- 基于verilog的异步fifo设计,仿真效果良好-asynchronous fifo based on zhe verilog language
sdh
- SDH是现代光纤通信中广泛应用的数据传输格式,在SDH帧结构中,前9列为开销字节,它包含了很多重要的信息,本程序为SDH开销的接收处理,查找帧头,分频,勤务话字节E1异步fifo。可拆为三段源代码,不知道能不能抵三个程序-SDH is a modern optical fiber communication is widely used in data transmission format, in the SDH frame structure, as the former 9 overhea
fifo
- 先入先出缓冲存储器,采用verilog hdl-FIFO buffer memory, using verilog hdl
AS_FIFO_DESIGN_Verilog
- 使用Verilog硬件描述语言完成了一个异步FIFO的设计,供相关硬件开发人员参考。-Verilog hardware descr iption language used to complete an asynchronous FIFO design, hardware development for the relevant reference.
Verilog_for_FIFO
- 利用Verilog语言进行FIFO设计,在FPGA中实现32X8FIFO功能-FIFO using Verilog language design, in the FPGA to achieve 32X8FIFO function
fifo
- 实现fifo的基本功能。使用Verilog能够实现的同步数据先入先出功能,简单易懂,并带有相应的测试文件-Fifo realize the basic functions. Be able to use the Verilog implementation of the synchronous data FIFO functions, easy to understand, with the corresponding test file
FIFO_Buffer
- Verilog的FIFO源代码,可综合,并以运用到具体工程中-Verilog source code of the FIFO can be integrated and applied to specific projects
fifo_test
- FIFO读写verilog程序,经本人验证,能够顺利运行。实现FPGA对fifo的控制。-the example of writing and reading the fifo ram of the fpag,i have already tested it.