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yima3_8
- 译码是编码的逆过程，它的功能是将具有特定含义的二进制码进行辨别，并转换成控制信号。此程序虽然简单，但能很好的理解用eril HDL语言设计组合逻辑电路的过程。-Decoding is the inverse process of encoding, and its function is to have a specific meaning to distinguish between binary code and converted into control signals. Althoug
VerilogHDL
- Veriolg HDL application for digital design
manchester_verilog
- 采用Verilog HDL语言编写的曼彻斯特码， 文件列表： help md.v md_tf.v me.v me_tf.v med.v-Using Verilog HDL language of the Manchester code, the file list: helpmd.vmd_tf.vme.vme_tf.vmed.v
create_new_component
- sopc 中，新建component。详细介绍了如何根据HDL代码生成黑盒的过程。-SOPC, the new component. Described in detail how the HDL code generation black-box process.
DSP
- 从算法设计到硬线逻辑的实现：复杂数字逻辑系统的Verilog HDL设计技术和方法，结合DSP算法介绍verilog HdL 设计。-From algorithm design to achieve hard-wired logic: complex digital logic system Verilog HDL design techniques and methods, combined with DSP algorithm design verilog HdL introduced.
fifo
- 先入先出缓冲存储器，采用verilog hdl-FIFO buffer memory, using verilog hdl
dds
- 直接频率合成器，采用verilog hdl-Direct frequency synthesizer using verilog hdl
ADC_16bit
- 模数变换器，采用verilog hdl编写-Analog-to-digital converters, used to prepare verilog hdl
VerilogHDL
- Verilog HDL 入门教程，可供参考。-Verilog HDL Started Guide is available for reference.
VHDLorverilogHDL
- 选择VHDL还是verilog HDL，说明文档-Choice of VHDL or verilog HDL, documentation
project_UHF_ddc
- vhdl语言写的数字下变频的实现，整个工程文件，xlinx ise用的-VHDL language written in the realization of digital down conversion, the whole project file, xlinx ise used
S8_VGA
- VGA的verilog hdl 程序，完成显示长条状显示不同颜色-VGA s verilog hdl procedures, completion of a long strip show show different color
add
- Verilog hdl语言 常用加法器设计，可使用modelsim进行仿真-Verilog hdl language commonly used adder design, can use the ModelSim simulation
GFmultiply
- Verilog hdl语言 伽罗华域GF（q）乘法器设计，可使用modelsim进行仿真-Language Verilog hdl Galois field GF (q) multiplier design, can use the ModelSim simulation
ABEL-HDL_Reference
- VHDL进行设计输入开发的工具，好东西，快下载-VHDL design input to develop a tool for good, fast download
1-in_clk
- Verilog HDL编写的4条指令CPU-Verilog HDL prepared four instructions CPU
745221frequency
- 用Verilog HDL / VHDL实现的数字频率计（完整实验报告）-Using Verilog HDL/VHDL realization of digital frequency meter (complete test report)
veriloghdl-135
- verilog hdl教程135例-verilog源码-verilog hdl Tutorial-verilog source 135 cases
disanci
- 5位的操作数X和Y输入后暂存在寄存器A和B中，两位的操作控制码control暂存在寄存器C中，按照control码的不同，分布实现下列操作： 00控制X+Y 01控制X-Y 10控制X and Y 11控制 X xor Y 运算结果暂存在寄存器D中，然后输出。 -5 of the operand X and Y after the temporary importation of A and B in the register, the two operational c