搜索资源列表
AlteraSDR-SDRAM
- Altera 官方提供的SDRAM控制器,verilog的-SDRAM controller provided by Altera in Verilog HDL
VerilogHDL
- Verilog HDL的开发学习教程。值得一看，学FPGA的朋友。-Verilog HDL Development Study Guide. Worth a visit, learn FPGA friends.
Writing_Efficient_Testbenches
- vhdl语言 和verilog hdl语言的测试程序编写- testbench for vhdl and verilog
verilogcode
- 这是用于xilinx virtex-2 pro产品的误码仪方案verilog HDL代码-verilog code for bit-error rate tester
LED2
- 采用Verilog hdl编程语言实现led显示，有工程代码用QII软件编译调试-led Verilog hdl
ldpc
- 最近在做毕设，ldpc码的编解码实现，这个是verilog实现。-Recently completed the set up to do, ldpc code codec implementation, this is the Verilog implementation.
Music_LiangZhu
- FPGA音乐试验，语言：verilog HDL-A FPGA expperientation which can play music Liangzhu，language：verilog HDL
verilog_tech
- 本文介绍Verilog HDL语言的发展历史和它的主要能力。并对各种使用进行详细讲解。-This article describes the development of Verilog HDL language and its history, the primary capacity. And explain in detail the various use.
can
- 基于Verilog HDL 的一个CAN总线IP核。-Based on Verilog HDL a CAN bus IP core.
veriloghdl_teaching_model
- Verilog HDL权威教程，建模实例及语法参考和其他论题- Authority Verilog HDL tutorials , modeling examples and reference grammar ，other topics.
SDRAMController
- 璁茶Вsdram鐨勬搷浣滐紝闄勬湁verilog hdl浠ｇ爜
CCD_DRIVER
- verilog HDL语言，线性CCD1501D驱动程序，基于FPGA，其他线性传感器可参照修改。-verilog HDL language, linear CCD1501D driver, based on the FPGA, the other linear sensor can be modified by reference.
NANDFLASH
- 用VHDL开发的NANDFLASH的读写程序,给出 NANDFLASH的时序正确的读写-NANDFLASH developed using VHDL to read and write the procedures, timing NANDFLASH give the correct reading and writing
UART_receiver
- 通用串口收发器的移位寄存器 是verilog hDl编写-uart_reg
altera_avalon_uart_init
- 用v-hdl写的基于fpga的串口驱动程序希望对大家有帮助-With v-hdl Writing FPGA-based serial driver would like to have everyone help
state_machine
- 基于pci的verolog hdl 状态机描述-Pci of verolog hdl-based state machine descr iption
sha256_512
- Verilog实现的SHA256/SHA512算法，已仿真和验证-Verilog implementation of SHA256/SHA512 algorithm, simulation and verification has been done.
clock
- 数字电子钟的Verilog HDL语言描述。-Digital electronic clock Verilog HDL language to describe.
chap12
- 16个常用HDL编码打包上传 包括记数器，多路选择器，全加/半加器等，均通过modsim验证-16 commonly used HDL coding package upload includes counter, MUX, all add/semi-add, etc., are adopted to verify modsim
lizi
- 王金明编著的数字系统设计关于另外一种通用硬件描述语言书上的所有例子-Wang Jinming edited the " Digital System Design and Verilog HDL" book on all the examples