搜索资源列表
clock
- 很好的多功能数字钟的HDL代码不可多得的哦-Good multi-function digital clock of the HDL code rare Oh
Verilog_Example
- 设计与验证Verilog_实例，经典的HDl书籍，强烈推荐-Design and verification Verilog_ examples Hdl classic books, strongly recommend
SOPC_pwm_source
- 在SOPC下制作自定义部件（PWM发生器）的源程序，包括硬件描述HDL文件和驱动程序文件-Produced in the SOPC custom component (PWM generator) of the source, including hardware descr iption HDL files and driver files
digi_clock.7z
- v.hdl檔的電子時鐘,只要請動sw就會開始顯示-v.hdl file an electronic clock, as long as the requested action will begin to show sw
usb20_ipcore_usb_funct
- usb的芯片ip core. 用HDL描述，适合asic/fpga人员参考或使用。USB ip core for ASIC/FPGA designers.-usb chips ip core. with HDL descr iption suitable for asic/fpga staff reference or use. USB ip core for ASIC/FPGA designers.
Serial
- FPGA与PC串口通信的Verilog HDL 程序-FPGA and the PC serial communication procedures Verilog HDL
jsq
- 本程序为24小时计时器，稳定无误差。简单好用，是Verilog HDL语言初学者的指引。-This procedure for 24-hour timer, stable error-free. Easy-to-use, is the Verilog HDL language beginners guide.
c15_add
- 精通verilog HDL语言编程源码之1--常用加法器设计-Proficient in programming language source verilog HDL of 1- Common adder design
c16_multiple
- 精通verilog HDL语言编程源码之2--常用乘法器设计-Proficient in verilog HDL source language programming of 2- Common Multiplier
c19_CICfilter
- 精通verilog HDL语言编程源码之5--CIC积分梳状滤波器设计-Proficient in verilog HDL source language programming of 5- CIC Integrator Comb Filter Design
c20_cordic_computer
- 精通verilog HDL语言编程源码之6--CORDIC数字计算机的设计-Proficient in language programming verilog HDL source of 6- CORDIC digital computer design
c23_RS_decoder
- 精通verilog HDL语言编程源码9——RS(204,188)译码器的设计-Proficient in verilog HDL source programming language 9- RS (204188) decoder design
FPGAandSOPC
- FPGA&SOPC快速入门教程(PDF)，基于Verilog HDL语言，开发环境Quartus-FPGA
seg7led
- Verilog HDL源码，显示器段数码管数字累加，测试通过-Verilog HDL source code, the display segment digital tube digital cumulative, testing through
pwm_avalon_interface
- altera 公司内部PWM的HDL及驱动代码-altera internal PWM and driver of the HDL code
PCR
- 本程序是在传输流传输过程中对节目时钟字段进行检测与修改,采用Verilog HDL 语言进行编程。-This procedure is in the transport stream during transmission of program the clock to carry out field testing and modification, using Verilog HDL language programming.
source
- verilog HDL example .many module .
fcsr
- 伪随机序列产生器－代进位反馈移位寄存器，verilog hdl 原代码。-Pseudo-random sequence generator- on behalf of binary feedback shift register, verilog hdl original code.
ffcsr
- 伪随机序列产生器－filtered 代进位反馈移位寄存器，verilog hdl 原代码。-Pseudo-random sequence generator-filtered on behalf of binary feedback shift register, verilog hdl original code.