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DS1820
- DS18B20单总线数字式温度传感器实验,实验连线时QD连P1.0,串并转换实验孔 DIN P3.0, CLK P3.1,LED两位显示,-DS18B20 single-bus digital temperature sensor experiment, experiment QD connection with P1.0, string and convert experimental hole DIN P3.0, CLK P3.1, LED 2 display,
serial_in
- verilog 串并转换程序 状态机 有4位前导码 共转换3位 可自己修改后转换更多的串行数据位-Verilog serial signal to parallel signal transfer
comport
- 接口程序的编写,串并转换。本程序在ISE集成开发环境下编写。适合初学者学习。-Interface program of preparation, string and conversion. The procedures in the preparation of ISE Integrated Development Environment. Suitable for beginners to learn
p_s
- 用Verilog HDL语言进行串并转换,并通过Quartus Ⅱ 功能仿真验证-Series with the Verilog HDL language and converted, and through functional simulation Quartus Ⅱ
chuanbing
- 串并转换器的verilog源代码带testbench文件-String and converter verilog testbench file with the source code
ser2par
- 采用verilog 硬件描述语言实现对数据进行串并转换-Using verilog hardware descr iption language implementation of the data string and convert
change
- 同步串并转换程序,1位串行输入,8位并行输出。-Synchronous series and the conversion process, a serial input, 8-bit parallel output.
OFDM
- OFDM下行的仿真1、产生要传输随机数; 2、进行调制; 3、串并转换; 4、进行IFFT操作(代码中有用到共轭对称向量的IFFT为实数进行简化计算); 5、增加循环前缀; 6、并串转换; 7、输出前滤波; 8、增加信道噪声(加性高斯白噪声); 9、接收端串并转换; 10、去除循环前缀; 11、进行FFT变换; 12、信号解调; 13、误比特率计算; -OFDM downlink simulation 1, have t
164
- 基于164实现串并转换,结合LED七段数码管实现一位计时器-164 series-based implementation and conversion, with seven segment LED digital timer to achieve a
uartin
- 串口通信,实现数据的串并转换,以及并串转换-Serial communication, serial and parallel data conversion, and parallel to serial conversion
OFDM
- 基于对比BPSK系统的OFDM仿真结果分析,把N个子载波上的传输符号通过IFFT,然后并串转换后传输,在接收端通过串并转换后再进行FFT变换-BPSK OFDM system based on comparative analysis of simulation results, the N sub-carrier transmission symbols by IFFT, and the string conversion and transmission, the receiver stri
8PSK
- 8PSK蒙特卡罗图分析,产生一个等概率且相互独立的二进制序列,将二进制序列通过串-并转换为一个三位码组。-8PSK Monte Carlo chart analysis, so the probability of generating a binary sequence and independent of each other, the binary sequence through series- and converted to a three code groups.
vhdl
- 串并转换和PN码产生的VHDL程序 希望对刚学习VHDL语言的同学有帮助!-And the PN code string and convert VHDL program generated just want students to learn VHDL, help!
Example-4-16
- 串并转换建模 数据流串并转换的实现方法多种多样,根据数据的排序和数量的要求,可以选用移位寄存器、RAM等来实现。对于数据量比较小的设计来说,可以使用移位寄存器完成串并转换;对于排列顺序有规定的串并转换,可以用case语句判断实现;对于复杂的串并转换,还可以用状态机实现-Modeling serial data stream and convert the realization of string and convert many ways, sort and quantity of the
www
- 主要功能就是实现基于FPGA的FIR滤波器设计的串并转换。-Main function is to implement FPGA-based FIR filter design and convert the string.
QDPSK
- qdpsk编码 以EDA进行编码,先进行串并转换 再转换编码-qdpsk encoding EDA encoded string and convert another first for transcoding
SP_convert
- 串并转换的代码,很不错,共享一下;共享万岁;-String and convert the code, very good about sharing very good
data_swith
- verilog 代码实现串并转换,有延迟-Verilog code and string conversion, delay
chuanbingzhuanhuan
- 可以实现串并转换功能,并且在modelsim6.0软件中成功仿真!-String and conversion functions can be achieved, and success in modelsim6.0 software emulation!
yiweijicunqi
- 移位寄存器实现串并转换,8位移位寄存器,具有一步复位,同步置数,同步清零-Serial shift register implementation and conversion, 8-bit shift register, with a further reduction, the number of synchronous set, synchronous clear