搜索资源列表
serial
- 串行口数据传输实验,vhdl源代码,完成信号发生,串并转换,检测电路
tushuguan
- --功能描述 --1 刷卡后产生与本人身份唯一对应的串行二进制码元序列,作为模拟系统的输入信号(此处不妨设为8位学生学号)。 --2 经过串并转换,序列变成一个8位二进制数。 --3 遍历预先存储在rom中的学号信息,逐一和这个8位数相比较,如果有相匹配的信息,显示欢迎字样(此处用一个高电平表示),同时打开栅栏门(也用一个高电平表示)。
sditest
- 基于ep3c25的altera sdi ip核的使用,串并转换和并串转换
5
- 串并转换程序,由串行输出转换为4位的并行输出
Verilog_serdes
- 用verilog写的串并转换程序,希望对大家有用!
pn_code
- 系数为4的扰码生成器,并每四位扰码产生一个触发串并转换的触发信号,可用于4b/5b编码的触发信号。verilog程序,带test程序-coefficient of the four scrambler generator, and every four scrambler have triggered a string conversion and the trigger signal can be used to trigger 4b/5b coding signal. Verilog pro
bsconvert
- 基于FPGA的实现数据串并转换的程序,可以把8位串行数据转换为8位并行数据,或把8位并行数据转换为8位串行数据等-FPGA-based string and data conversion procedures, can be 8-bit serial data into 8-bit parallel data, or the 8-bit 8-bit parallel data into serial data
ps
- VHDL语言编写的串并转换模块的源代码,用来将并行输入数据转换为串行数据输出-code for the transform of ps
FPGA-design-ideas-and-techniques
- FPGA 设计的四种常用思想与技巧包括:乒乓操作,流水线操作,串并转换技巧,数据接口同步方法-The four commonly used FPGA design ideas and techniques include: ping-pong operation, pipelining, and convert the string technique, synchronous data interface methods
HDLC
- hdlc设计,包括flag检测,插0、串并转换等设计,采用verilog编程。-hdlc design, using verilog
ppfilter
- QAM调制函数,对产生的二进制数进行qam调制,调制原理是对产生的二进制数进行串并转换,然后分为两路再进行qpsk调制-QAM modulation function, the resulting binary number for QAM modulation, modulation principle is generated binary number and converted to string, and then further divided into two QPSK modul
cdma-matlab
- 用matlab程序模拟实现cdma系统的整个过程。包括并串、串并转换,m序列的产生,直接扩频、解扩,qpsk的调制解调,载波调制解调等。-Matlab simulation procedures used to achieve the whole process of cdma systems. Including and string SERDES, m sequence generation, direct spread spectrum, despreading, qpsk the mod
alaw
- 使用VHDL实现通信脉冲编码调制(PCM)中的a律转换,并实现串并、并串转换。-Use VHDL to achieve communication pulse code modulation (PCM) of a law conversion, and to achieve and string, and string conversion.
keydisplay
- 单片机显示程序 采用键盘输入 定时器中断 串并转换 功能强大 有电路原理图 和源码-Single-chip display program using keyboard input timer interrupt powerful SERDES circuit schematic and source code
bingchuan2
- verilogHDL编写的并串转换模块,在ISE软件中仿真过,可综合,绝对是正确的-prepared and verilogHDL string conversion module, the ISE simulation software that can be integrated, is absolutely correct
SerialtoParallel
- proteus仿真74164串并转换,显示跑马灯-proteus SERDES 74,164 simulation shows Marquee
chuankou
- 系统上电复位后,系统就处于等待状态,当K0到K7有按键动作时,单片机会将动作的按键号0到7串行发送到串并转换芯片74LS164中,芯片74LS164使74LS240驱动数码管显示按键所对应的按键号。-System power-on reset, the system in a wait state, when there are key K0 to K7 action, single-chip will be the key actions 0-7 serial number is sent t
74hc595
- 74HC595的汇编源代码,串并转换可省不少单片机口线.附595的规格书.-74HC595 compilation of source code, SERDES I can save a lot of single-chip line. 595 of the specifications attached.
key_scan
- 非常实用的单片机键盘扫描程序,含常规行列扫描,通过74LS164或74HC595的串并转换后的行列扫描,以及通过TLC1543后的A/D转换后的直读扫描,再有常规的直读扫描,程序中含有记忆算法。-Very practical single-chip scanner keyboard, with the ranks of conventional scanning, 74LS164 or 74HC595 through the string and the ranks of the post-co
s2p
- 一个很好的串并转换verilog代码,带有modelsim仿真文件-very good