搜索资源列表
BMalthorithm
- BM算法找出产生该段序列的最短级数的线性反馈移位寄存器（LFSR)，如对序列a=(1001101011),结果为LFSR(25,4)即周期为25，寄存器级数为4，此处所给为固定长度。-Using BM algorithm to find the linear feedback shift registers with the least steps corresponding to certain sequence. For example, as for a=(1001101011), the
gen_displayer
- 基于线性反馈移位寄存器电路，并结合FPGA 的特有结构，一种简捷而又高效的伪随机序列产生方法-The Implementation and Research on Pseudo-Random Number Generators with FPGA
lfsr
- 伪随机序列产生器－线性反馈移位寄存器，Verilog HDL 原代码。-Pseudo-random sequence generator- linear feedback shift register, Verilog HDL source code.
juanjima
- 卷积码的生成程序,为(2,1,3)移位寄存器的卷积码生成-Convolutional code generation process for the (2,1,3) convolutional code of the shift register to generate
verilog
- Verilog桶形移位寄存器，实现不溢出移位-Verilog barrel shift register, the shift towards non-overflow
LFSR
- 简单的线性反馈移位寄存器标准C语言实现，采用visual c++2010编写，如果你打不开，请复制里面的.cpp文件采用visual c++6.0打开即可。 详细内容见源码-Simple linear feedback shift register the standard C language, written with visual c++2010, and if you can not open, please copy the inside. Cpp file using visua
Sequence-detector-design
- 序列检测器设计的思路大多都是用FSM来实现的,此思路是通过移位寄存器来实现序列检测-Sequence detector design ideas are often used to achieve the FSM, the idea is to achieve through the shift register sequence detection
HDB3
- 用verilog HDL语言，通过一个4位移位寄存器实现一个信号转化为HDB3码并进行测试 -Using verilog HDL language, through a 4-bit shift register realization of a signal into HDB3 code and test
Berlekamp_Massey
- 移位寄存器中的基础算法，Berlekamp Massey算法-The basis of the shift register algorithm, Berlekamp Massey algorithm
LFSR
- verilog实现的8阶伪随机序列发生器，文件包含了三种主要模块：控制模块，ROM模块，线性反馈移位寄存器（LFSR）模块。已经通过modelsim仿真验证。-verilog to achieve 8-order pseudo-random sequence generator, the file contains three main modules: control module, ROM modules, a linear feedback shift register (LFSR) mo
LXY28161-EN
- 零星雨16位恒流移位寄存器手册，零星雨16位恒流移位寄存器手册-Constant current shift registers Manual 16 sporadic rain, sporadic rain 16 constant current shift register
PRBS
- 用带反馈通道的移位寄存器产生PRBS序列信号。要选择合适的通道，经模二加法后进行反馈。在程序中，移位寄存器个数可从2到13中任意选择，其长度也可以自由选择。运行结果在vc++的运行环境中能看得很清楚，最后产生的M序列数据也存在相应的数据文件中。-Used with feedback channel shift register sequence generated PRBS signal. Please select the appropriate channels, by mode after
LFSR
- 伪随机序列产生器,线性反馈移位寄存器，原代码。-Pseudo-random sequence generator, linear feedback shift register, the original code.
ffcsr
- 伪随机序列产生器－filtered 代进位反馈移位寄存器，verilog hdl 原代码。-Pseudo-random sequence generator-filtered on behalf of binary feedback shift register, verilog hdl original code.
fcsr
- 伪随机序列产生器－代进位反馈移位寄存器，matlab 原代码。-Pseudo-random sequence generator- on behalf of binary feedback shift register, matlab source code.
ffcsr
- 伪随机序列产生器－filtered 代进位反馈移位寄存器，matlab 原代码。-Pseudo-random sequence generator-filtered on behalf of binary feedback shift register, matlab source code.
ffcsr
- 伪随机序列产生器－代进位反馈移位寄存器，电子书。-Pseudo-random sequence generator- on behalf of binary feedback shift register, e-books.
R
- 双向移位寄存器的原理设计程序，对于初学者将会有很大帮助，尤其在设计功能比较复杂的FPGA时，有些问题其实用这个就很简单-The principle of bi-directional shift register the design process, for beginners there will be a great help, especially in the design features of the FPGA more complex, there are some proble
VHDL1
- 移位寄存器和9人表决器电路的VHDL设计方案-Shift register people to vote and 9 of VHDL circuit design
16X64dianzhen
- 16*64点阵程序，运用串行传输数据，移位寄存器接收数据，硬件电路连接简单-16* 64 lattice procedures, the use of serial transmission of data, receive data shift register, hardware circuits connected simple