资源列表
华为_FPGA设计高级技巧Xilinx篇
- 华为FPGA设计高级技巧Xilinx篇 华为FPGA设计 verilog语言(HuaWei FPGA Advanced design techniques Xilinx)
Vivado 简明教程
- vivado简明教程 vivado入门教程 vivado简易教程(vivado API Tutorial Vivado)
华为_FPGA设计流程指南
- 华为_FPGA设计流程指南 FPGA设计入门教程(Huawei FPGA Design process guide)
LIFO_Spartan3
- The code for a LIFO in verilog
Clock generator
- A clock Generator in verilog
Chapter 4
- codes and simulation of chapter 4
Chapter 8
- verilog code and simulationsof chapter4
src
- Digit serial adder, can be used in digital filter design You can choose the pipeline length, digit size and the word length of the adder.
PmodHMT
- Demo 使用 PmodHMT 模块实时检测环境温度和湿度。(The Demo uses PmodHMT modules to detect environmental temperature and humidity in real time.)
xa880
- Join repetitive control, Very convenient to use, Iterative self-organizing data analysis.
full_license
- quartus9.0 全功能license(quartus9.0 full license)
VHDL——如何写简单的testbench
- 基于VHDL的testbench编写攻略(VHDL based on the preparation of testbench Raiders)