资源列表
xapp1052
- ML605开发版 生成IP核的时候选择250MHZ pcie2.0 X4 5Gb/s 其他参考PDF文档。(When the ML605 development version generates the IP kernel, select 250MHZ pcie2.0 X4 5Gb/s Other reference PDF documents.)
UART-Altera
- 使用Atera FPGA CycloneII 实现串口通信，遵循RS232协议。FPGA上的模块实现了数据的接收，取补码和发送。(Achieve serial communication with FPGA, following the protocol of RS232.)
I2C总线协议中文版PDF
- fpga的I2C设计文档，VERILOG语言，I2C协议(FPGA I2C design documents, VERILOG language, I2C protocol)
usb_veriloghdl
- USB是 FPGA设计，verilog语言实现(USB is FPGA design, Verilog language implementation)
3des_vhdl
- 3DES VHDL SOURCE CODE
clock
- 基于verilog简易数字钟，能够做到计时，闹钟，倒计时等功能。(Based on Verilog simple digital clock, can achieve time, alarm clock, countdown and other functions.)
fpga很有价值的27实例
- 为fpga初学者设计的基于fpga的27个简单实用的应用实例，(FPGA Application example)
dds1
- 通过FPGA实现的，dds数字信号发生器，可产生正弦波，方波，锯齿波，三角波(DDS digital signal generator through FPGA, DDS digital signal generator, can produce sine wave, square wave, sawtooth wave, triangle wave)
123
- 3路输入，8路输出的译码器，利用FPGA,BASYS3板子实现该功能，文件已有源代码，仿真代码和约束文件。(3 way input, 8 way output decoder, using FPGA, BASYS3 board to achieve the function, the document already has source code, simulation code and constraint files.)
fir
- 基于verilog的 FIR低通滤波器的实现(Implementation of FIR low pass filter based on Verilog)
modelsim_10.1d破解工具
- modelsim_10.1d破解工具 modelsim_10.1d破解工具(modelsim_10.1d crack tools)
add
- verilog实现的完整的加法器，包括测试文件等(Verilog implements a complete adder, including test files)