资源列表
fadder_1
- 利用quartus9.0编写的半加器程序，自己亲手设计，能有效运行出结果(Quartus9.0 prepared by the semi adder program, personally designed to effectively run the results)
hadder_1
- 用quartus9.0编写的一位全加器，自己设计，能有效运行出结果(Written in quartus9.0 with a full adder, their own design, can effectively run the results)
fadder_4
- 利用quartus9.0中元器件模块设计的四位全加器，能运行出结果(Quartus9.0 binary device using the design of four bit full adder, can run the results)
fadder_4v
- 利用quartus9.0中verilog语言实现的四位全加器，亲测有效(Using quartus9.0 Verilog language to achieve the four bit full adder, pro test effective)
pipelined_fft_256
- verilog编写的并行256点fft代码(Verilog prepared parallel 256 points fft code)
adaptive_lms_equalizer
- 自适应算法的verilog实现，是一个很好的学习例子(The adaptive algorithm verilog implementation is a good example of learning)
dds_synthesizer
- Verilog编写的基于DDS的信号发生器，频率可变。(Verilog prepared by the DDS-based signal generator, the frequency variable.)
PllTwoOrder
- Verilog编写的二阶锁相环代码，环路可以收敛。(Verilog prepared by the second-order phase-locked loop code, the loop can converge.)
E8_1_RS232
- VHDL编写的RS232串口通讯代码，可以使用。(VHDL prepared by the RS232 serial communication code, you can use.)
E7_2_IntBitSync
- 位同步的VHDL实现，代码可综合。很好用！(Bit synchronization of the VHDL implementation, the code can be integrated. very useful!)
Mtk_Res1.4
- mn mnbmnbmnbmbmnbmb
mingmie-V4.1
- Based on the time delay estimation of power spectrum, Based on piecewise nonlinear weight value Pso algorithm, Machine learning routines.