资源列表
code.sources
- 秒表代码加上相应的key，测试通过可以直接用于vivado(zcscscsasfsdfsfasfasf)
Verilog HDL（第4版）[王金明][电子教案]
- Verilog HDL（第4版）[王金明][电子教案].rar 注意是ppt教案。(Verilog HDL (Fourth Edition) [] [Wang Jinming].rar e-lesson plans note ppt plans.)
src
- 使用FPGA+DAC产生DDS，可变频率(user FPGA and DAC generate DDS)
pinlvxianshi
- 通过FPGA中的时钟信号分频作为基准频率，将另一频率作为输入与之比较，并在数码管显示输入频率。(The frequency division of the clock signal in the FPGA is used as the reference frequency, the other frequency is used as input, and the input frequency is displayed in the digital tube.)
CNTlum
- 使用Windows7 系统，quartus ii 9.1 软件，Verilog 语言 0到9的计数，并且亮度逐渐增大(count from 0 to 9,and the lum become more and more high)
jisuan
- 51单片机按键式计算机,可以进行简单的加减乘除计算，使用方便(my English very bad,so I don't write)
SystemVerilog 验证方法学
- systemverilog 验证方法学，夏宇闻版(systemverilog verification methodology)
ALU
- 算术逻辑单元,可以实现加法、减法、比较、移位、与门、或门等功能(arithmetic and logic unit)
uart
- FPGA串口通信能在实现字符数据传输，与stm32中的串口通信类似(FPGA serial communication, in the realization of character data transmission, and STM32 serial communication similar)
4LED
- 4LED流水灯程序，可更换频率，采用状态机，低电平有效亮灯，高电平熄灭(4LED water lamp program, you can change the frequency. Using state machine, low level active light, high level extinction)
top1
- 七段数码管译码器，可显示0~9共10个字符。(Seven segment digital decoder, 0~9 can display a total of 10 characters.)
CLOCK
- 时钟，带闹钟设置，整点报时功能，闹钟带有停止键(Clock, with alarm set, the whole point timekeeping function, alarm clock with stop button)