资源列表
FIFO_RAM
- 同步FIFO_RAM的设计及其testbench(8 bit SYN FIFO module fifo_v(clk,rst,wen,ren,full,empty,data,q);)
pn10
- 用verilog生成11级的pn序列，Xilinx平台(Generating 11 levels of PN sequences with Verilog)
CMI
- CMI编码原理图，可以通过对m5随即序列进行编码和解码(CMI is designed for m5 random list, which is should in the project, and it can decode it and get the original m5 list)
Songer
- 梁祝音乐演奏，用fpga器件驱动小扬声器构成一个乐曲演奏电路(Butterfly Lovers music performance)
piano
- 电子琴 原创 作业 VHDL 采用计数器分频，内含简单儿歌数首，爱迪克ＥＤＡ实验箱，有数码管与ＬＥＤ显示，采用键盘式输出，两行，中音高音。(Electronic piano original work VHDL, using counter frequency division, contains a few simple nursery rhyme, Edik EDA experimental box, there are digital tube and LED display, usin
crc16
- 一个实现CRC16的VHDL代码，以及说明CRC计算的原理和方法。(a VHDL code for CRC16.)
SDI资料
- xilinx官方资料 学习sdi很好的入门资料(Xilinx official information, , a good introductory information for learning SDI)
vivado
- vivado 2016.1 license 亲测可用(vivado 2016.1 & license)
test1
- 七段译码器的verilog语言程序，功能由七根二极管来显示0到9数字的东西，就是显示器(seven-segment decoder)
fpga代码
- 实现了m序列产生，同步信号提取功能，实现了所有功能(The m sequence is generated and the synchronous signal extraction function is realized)
AD9512_test
- 该程序包实现时钟芯片AD9512调试，完整的程序包(Clock chip AD9512 debugging, achieve use successfully)
PWM
- VHDL code for PWM Generator with Variable Duty Cycle