资源列表
8个数码管显示数码管动态扫描显示
- 共阳极数码管显示1,2,3,4,5,6,7,8。FPGA可直接编译。
fec
- RS编码电路 ，包括乘法器的模块和编码部分 RS编码器\mula_0.v RS编码器\mula_1.v RS编码器\rscode.v(The RS encoding circuit includes a multiplier module and an encoding section RS encoder \mula_0.v RS encoder, \mula_1.v, RS encoder, \rscode.v)
mux41
- 四选一数据选择器（四个输入选择一个输出）(Four select a data selector)
vivado_init
- 该程序是为vivado初始化和配置，并且还包含有相应的说明文档，是初学xilinx vivado的很好的教程，本例程基于zynq系列的MIZ701N处理器进行开发(The program is vivado initialization and configuration, and also contains the corresponding documentation, is a good beginner Xilinx vivado tutorial, this routine based
???
- This is timer code using VHDL
1
- 一触即发 好玩的效果，基于quartus平台编写(This is a course work, showing some interesting results, welcome to download the exchange)
uart
- 带有fifo的功能模块，具有发送模块和接收功能模块(The function module with FIFO has transmitting module and receiving function module)
DPSK调制解调VHDL程序
- 用于DPSK的调制解调 包括码型变换及反变换过程(Modulation and demodulation for DPSK, including code type conversion and inverse transformation process)
IEEE Standard for Verilog 2005
- IEEE Standard for Verilog 2005
RAM2048X8
- you can add this code to your project if you need RAM2048X8
hp and lp filter
- hp and lp filter verilog code..
16x 16 vedic mulbit
- vedic 16x16 design and teshbench fully working codes..