资源列表
crc_unit_16
- 用verilog语言实现CRC16校验，已通过仿真验证。-Use verilog language implementation CRC16 calibration, was validated by simulation
mmm
- trhrthw rrh ryhsr hththaet haraefcergstt - trhrthw thw rrh ryhsr hththaet haraefcergstt
multi
- tr stgae farf af afadfczdc ar a faf
vga
- rewrsr r e et ysetysetstst sthss
responder
- basys2实现抢答器，Verilog描述语言，实现4人抢答器，功能已验证-Basys2 u5B9 u73B0 u62A2 u7B54 u5668 uFF0CVerilog u63CF u8FF0 u8BED u8A09 uFF0C u5B9E u73B04 u4EBA u62A2 u7B54 u5668 uFF0C u529F u80FD u5DF2 u9A8C u8BC1
VGA
- VGA接口，提供简单的行场扫描，和一个简单的色块例子-VGA interface, providing simple line scan, and a simple example of color blocks
Freq_gen
- VHDL语音写的标准分频模块，在vivado开发环境下运行-VHDL voice write standard frequency module, run in vivado development environment
rs232
- 基于RS232的串口传输程序，开发环境为vivado-RS232-based serial transmission procedures, the development environment for vivado
Watch
- FPGA开发板的简易时钟源码，开发环境为vivado-FPGA development board of the simple clock source, the development environment for vivado
VGA-(1)
- 基于FPGA的VGA接口代码，引脚已按装好，板子DE2-115-Based on FPGA of VGA interface code, the pin has been installed, board de2
key_debounce
- 按键消抖操作，采用计数延时20ms的方式实现按键消抖，防止出现误按，VHDL和verilog-Button shaking operation, the use of counting delay 20ms way to achieve the key to shake, to prevent the error, VHDL and verilog
FPGAshumaguan
- 基于FPGA设计的，可以实现数码管显示的程序-Based on FPGA design, the program of digital tube display can be realized